System and Method for Fast Walsh Transform Processing in a Multi-Coded Signal Environment

Abstract

A flexible Fast Walsh Transform circuit provides configurable FWT sizes, and is suitable for use in radio receivers where the received signal may be generated using varying spreading codes and/or varying numbers of multi-codes. Such signal types are commonly encountered in wireless communication systems like those based on the Wideband CDMA (W-CDMA) or IS-2000 (cdma2000) standards, and particularly with the higher data rate provisions of those standards. In one application, a RAKE receiver includes RAKE fingers that each include one of the flexible FWT circuits, such that each finger despreads the received signal using variably sized FWTs in accordance with the characteristics of the received signal. The flexibility in FWT sizing may derive from, for example, the inclusion of separately selectable but differently sized FWT circuits, or from the inclusion of a configurable FWT circuit capable of generating different sizes of FWTs.

1 . A pass-through butterfly (PTB) circuit to selectively perform a two-point Fast Walsh Transform (FWT) on first and second values, the PTB circuit comprising: 
 a first node to output a sum of the first and second values in a first mode and to output the first value in a second mode; and    a second node to output a difference of the first and second values in the first mode and to output the second value in the second mode.    
   
   
       2 . The PTB circuit of  claim 1 , wherein the first node is a summing circuit comprising: 
 an adder receiving the first and second values and outputting the sum of the first and second values; and    a switch operative to output the sum of the first and second values in the first mode and to output the first value in the second mode.    
   
   
       3 . The PTB circuit of  claim 1 , wherein the first node is a summing circuit comprising: 
 an adder receiving the first and second values in the first mode and receiving the first value and a null value in the second mode, such that the adder outputs the sum of the first and second values in the first mode and outputs the first value in the second mode; and    a switch operative to provide the second value to the adder in the first mode and operative to provide the null value to the adder in the second mode.    
   
   
       4 . The PTB circuit of  claim 1 , wherein the second node is a difference circuit comprising: 
 an adder receiving the first value and a negated second value and outputting a sum of the first and negated second values;    an inverter receiving the second value and outputting the negated second value; and    a switch operative to output the sum of the first and negated second values in the first mode and to output the second value in the second mode.