Integrated Circuit Chip With Repeater Flops and Method for Automated Design of Same

Abstract

An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

1 . An integrated circuit (IC) chip, comprising: 
 a plurality of physical tiles including a first tile and a second tile;    an interface configured to carry a signal from the first tile to the second tile;    wherein the interface includes a series of repeaters for carrying the signal in a pipelined fashion; and    wherein each of the repeaters includes at least one of (i) a flip-flop and (ii) a flip-flop coupled with an associated buffer.    
   
   
       2 . The IC chip of  claim 1 , wherein the interface is representative of a number of stages between the first tile and the second tile.  
   
   
       3 . The IC chip of  claim 2 , wherein each stage is configured to carry a different phase of the signal.  
   
   
       4 . The IC chip of  claim 1 , wherein the signal travels from one repeater to another repeater within the series of repeaters in synchronism with a clock cycle.  
   
   
       5 . The IC chip of  claim 1 , wherein each tile (i) includes at least one clock and (ii) is associated with a respective subset of the series of repeaters, the at least one clock being associated only with the respective subset of the series of repeaters.  
   
   
       6 . The IC chip of  claim 5 , wherein the respective subset includes at least two repeaters.  
   
   
       7 . A method for automated allocation and insertion of repeaters into a physical design of an integrated circuit (IC) chip, comprising: 
 receiving logical rules regarding a number of repeaters to be inserted between the first and second tiles; and    allocating and inserting repeaters into a physical design of the IC chip based at least in part on a determined distance and the logical rules.    
   
   
       8 . The method of  claim 7 , further comprising determining the distance that a signal must be driven from a first tile to a second tile in the physical design of the IC chip, the determining using at least one from the group including (i) an automatic calculation and (ii) a user provided input.  
   
   
       9 . The method of  claim 8 , further comprising uniquely associating at least one clock to particular sets of the repeaters.  
   
   
       10 . The method of  claim 9 , further comprising allocating and inserting repeaters into the physical design based upon an association of multiple interfaces through rules.  
   
   
       11 . The method of  claim 10 , wherein the allocation and inserting considers frozen tiles.  
   
   
       12 . An apparatus for automated allocation and insertion of repeaters into a physical design of an integrated circuit (IC) chip, comprising: 
 means for receiving logical rules regarding a number of repeaters to be inserted between the first and second tiles; and    means for allocating and inserting repeaters into the physical design of the IC chip based at least in part on a determined distance and the logical rules.    
   
   
       13 . The apparatus of  claim 12 , further comprising means for determining the distance that a signal must be driven from a first tile to a second tile following a route that is automatically or user generated in the physical design of the IC chip, wherein the means for determining uses at least one from the group including (i) an automatic calculation and (ii) a user provided input.  
   
   
       14 . The apparatus of  claim 13 , further comprising means for uniquely associating at least one clock to particular sets of the repeaters.  
   
   
       15 . The apparatus of  claim 14 , further comprising mean for allocating and inserting repeaters into the physical design based upon an association of multiple interfaces through rules.  
   
   
       16 . The apparatus of  claim 15 , wherein the means for allocating and inserting considers frozen tiles.  
   
   
       17 . A computer readable medium carrying one or more sequences of one or more instructions for execution by one or more processors to perform a method for automated allocation and insertion of repeaters into a physical design of an integrated circuit (IC) chip, comprising: 
 receiving logical rules regarding a number of repeaters to be inserted between the first and second tiles; and    allocating and inserting repeaters into the physical design of the IC chip based at least in part on a determined distance and the logical rules.    
   
   
       18 . The computer readable medium of  claim 17 , further comprising determining the distance that a signal must be driven from a first tile to a second tile in the physical design of the IC chip, the determining being based upon at least one from the group including (i) an automatic calculation and (ii) a user provided input.  
   
   
       19 . The computer readable medium of  claim 18 , further comprising uniquely associating at least one clock to particular sets of the repeaters.  
   
   
       20 . The computer readable medium of  claim 19 , further comprising allocating and inserting repeaters into the physical design based upon an association of multiple interfaces through rules.  
   
   
       21 . The computer readable medium of  claim 20 , wherein the allocation and inserting considers frozen tiles.  
   
   
       22 . A computer readable medium carrying one or more sequences of one or more instructions for execution by one or more processors to perform a method of manufacturing an integrated circuit (IC) chip, comprising: 
 identifying pipeline stages for interconnecting logic modules within the IC; and    simulating a functionality of the pipeline stages.    
   
   
       23 . The computer readable medium of  claim 22 , wherein the simulation is a logical simulation.  
   
   
       24 . The computer readable medium of  claim 22 , further comprising translating results of the simulated functionality into a physical implementation.  
   
   
       25 . A method for operating an integrated circuit (IC) chip including two or more modules, each module including two or more repeater flops, the method, comprising: 
 providing two more timing schemes, each being common to corresponding ones of the two or more repeater flops from the two or more modules;    wherein signals received within at least one of the modules are associated with a respective one of the timing schemes.    
   
   
       26 . The method of  claim 25 , wherein each of the corresponding ones of the two or more repeaters is associated with a unique clock signal.  
   
   
       27 . A device comprising: 
 a first logic module including first and second repeater flops, each repeater flop including a flip flop coupled to a buffer, the buffer being configured to drive a signal provided as an input to the flip flop; and    first and second clocks, each being associated with a respective one of the repeater flops.    
   
   
       28 . The device of  claim 27 , further comprising a second logic module including first and second repeater flops; 
 wherein each of the first and second repeater flops of the second logic module is associated with a corresponding one of the first and second clocks.