Frequency divider monitor of phase lock loop

Abstract

A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

1 . A circuit comprising: 
 a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of said voltage controlled oscillator connected to an input of said feedback frequency divider, an output of said feedback frequency divider coupled to an input of said voltage controlled oscillator;    a frequency divider monitor having a first input, a second input and an output, said first input of said frequency divider monitor connected to said output of said voltage controlled oscillator and said second input of said frequency divider monitor coupled to an output of said feedback frequency divider; and    said frequency divider monitor including: 
 a first and a second period generator, each said period generator having an input and an output, said input of said first period generator is said first input of said frequency divider monitor and said input of said second period generator is said second input of said frequency divider monitor;  
 a first and a second period to voltage converter, each period to voltage converter having an input and an output, said input of said first period to voltage converter connected to said output of said first period generator and said input of said second period to voltage converter connected to said output of said second period generator;  
 an error amplifier having a first input, a second input and an output, said output of said first period to voltage converter connected to said first input of said error amplifier and said output of said second period to voltage converter connected to said second input of said error amplifier; and  
 a comparator having an input and an output and a plurality of threshold voltage inputs, said output of said error amplifier connected to said input of said comparator.  
   
   
   
       2 . The circuit of  claim 1 , wherein said first and second period generators are one-bit counters.  
   
   
       3 . The circuit of  claim 1 , wherein said first and second period to voltage converters each have a plurality of finger inputs and are identically designed current mirrors, a primary side of each current mirror comprising a current source and a secondary side of each current mirror comprising a plurality of fingers, corresponding fingers of said first and second current mirrors connected to a same corresponding and different finger input of said plurality of finger inputs.  
   
   
       4 . The circuit of  claim 1 , wherein said first and second period to voltage converters are identically designed current mirrors, a primary side of each current mirror comprising a current source and a secondary side of each current mirror comprising a plurality of fingers, each finger including a capacitor, corresponding fingers of said first and second current mirrors connected to a same corresponding and different finger input of said plurality of finger inputs.  
   
   
       5 . The circuit of  claim 1 , wherein said first and second period to voltage converters are identically designed current mirrors, a primary side of each current mirror comprising a current source and a secondary side, a first section of said secondary side of each current mirror comprising a first plurality of fingers, a second section of said secondary side of each current mirror comprising a second plurality of fingers, each finger of said second plurality of fingers including a capacitor, each finger of said first and second plurality of fingers connected to a corresponding and different finger input of said plurality of finger inputs.  
   
   
       6 . The circuit of  claim 1 , wherein said error amplifier is a peak voltage difference amplifier or an average voltage difference amplifier.  
   
   
       7 . The circuit of  claim 1 , further including: 
 a logic unit having an input and an output, said output of said comparator connected to said input of said logic unit, said output of said logic unit is said output of said frequency divider monitor.    
   
   
       8 . The circuit of  claim 1 , wherein: 
 said output of said voltage controlled oscillator is directly connected to said input of said feedback frequency divider;    said output of said voltage controlled oscillator is coupled to an input of a forward frequency divider, and an output of said forward frequency divider is coupled to said input of said feedback frequency divider; or    said output of said voltage controlled oscillator is coupled to said input of said forward frequency divider, said output of said forward frequency divider is coupled to an input of an external frequency divider, and an output of said external frequency divider is coupled to said input of said feedback frequency divider.    
   
   
       9 . The circuit of  claim 1 , said frequency divider monitor further including a decoder, said decoder responsive to a signal indicating a designed ratio of a frequency of a signal on said output of said voltage controlled oscillator and of a frequency of a signal on said output of said feedback frequency oscillator, said decoder having a first set of outputs connected to programmable inputs said first period to voltage converter and a second set of outputs connected to programmable inputs said first period to voltage converter.