MOS transistor device structure combining Si-trench and field plate structures for high voltage device

Abstract

A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field; therefore the transistor device has a relatively small size.

1 . A method of manufacturing a high voltage semiconductor transistor device, comprising: 
 providing a substrate of a first conductivity type;    forming a plurality of trenches comprising sidewalls and bottoms in the substrate;    performing a local oxidation of silicon (LOCOS) process on the sidewalls and bottoms of the trenches and on the substrate near the trenches to form a first field oxide region combined with the trenches, such that the first field oxide region has a lower surface in a shape of a plurality of protrusions;    forming a deep well of a second conductive type in the substrate;    forming a source diffusion region and a drain diffusion region respectively, wherein the first field oxide region is positioned between the source diffusion region and the drain diffusion region;    forming a gate dielectric layer on the source diffusion region;    forming a gate on the gate dielectric layer to laterally extend onto the first field oxide region; and    forming a plurality of field plates corresponding to the trenches.    
   
   
       2 . The method of  claim 1 , wherein forming a gate on the gate dielectric layer to laterally extend onto the first field oxide region and forming a plurality of field plates corresponding to the trenches are performed simultaneously.  
   
   
       3 . The method of  claim 1 , wherein the trenches retain an opening space after performing a local oxidation of silicon (LOCOS) process, and the field plates are formed in the trenches.  
   
   
       4 . The method of  claim 1 , further forming a first conductive type doped region in the deep well and a heavy first conductive type doped region in the first conductive type doped region, and the source diffusion region is formed by forming a heavy second conductive type doped region adjacent to the first conductive type doped region.  
   
   
       5 . The method of  claim 1 , wherein the drain diffusion region is formed by forming a light second conductive type doped region and forming a heavy second conductive type doped region within the light second conductive type doped region.  
   
   
       6 . The method of  claim 1 , further forming a guard ring structure at a periphery of the high voltage semiconductor device.  
   
   
       7 . The method of  claim 6 , wherein further forming the guard ring structure at a periphery of the high voltage semiconductor device comprising: 
 forming two second field oxide regions spaced apart each other at the periphery of the high voltage semiconductor device, and    forming an ion doped region in the substrate of the first conductive type between the second field oxide regions.    
   
   
       8 . The method of  claim 7 , wherein forming two second field oxide regions spaced apart each other at the periphery of the high voltage semiconductor device is performed simultaneously with the formation of the first field oxide region.