Non-volatile electrically alterable memory cells for storing multiple data

Abstract

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

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       6 . An electrically alterable non-volatile memory structure, comprising: 
 a first bit line;    a second bit line;    a shallow trench isolation region;    a first memory string and a second memory string, each memory string comprising: 
 a plurality of memory devices connected in parallel between a first end and a second end of the memory string, each memory cell having a first floating gate and a second floating gate; storing a plurality of data, each memory device having a first end and a second end;  
 a first diffusion region is provided in the memory string connecting the memory devices, the first diffusion region being provided adjacent the first floating gate of each memory cell;  
 a second diffusion region, spaced-apart from the first diffusion region, is provided in the memory string connecting the memory devices, the second diffusion region being provided adjacent the second floating gate of each memory cell;  
   a first select transistor selectably connecting the first diffusion region to the first bit line; and    a second select transistor selectable connecting to the second diffusion region to the second bit line; and    wherein the first diffusion region of the first memory string is isolated from the second diffusion region of the second memory string by the shallow trench isolation region.    
   
   
       7 . The memory structure of  claim 6 , each memory cell being capable of storing data in any one of four logic states.  
   
   
       8 . The memory structure of  claim 6 , each memory cell being capable of storing data in any lone of a plurality of logic states.  
   
   
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