Apparatus for efficient lfsr in a simd processor

Abstract

The apparatus provides for efficient implementation of multiple-bit leap-forward LFSR calculation in a SIMD processor. This provides an accelerated and programmable way to implement LFSR calculations in a SIMD processor. Conditional vector exclusive-OR accumulation is used by manipulating the leap-forward matrix, whereby one conditional vector exclusive-OR operation is performed for each column and partial results are accumulated. For an N-wide SIMD this results in close to N times acceleration of leap-forward LFSR calculation without additional resources or dedicated logic.

I claim:  
     
         1 . A SIMD processor core for performing vector operations comprising: 
 a) a set of vector registers wherein each vector register comprises N elements wherein the N elements comprising parts of one-dimensional vector and a two-dimensional array and said set of vector registers are grouped together and are operably coupled to a plurality of read ports and plurality of write ports for accessing said set of vector registers at substantially the same time; and    b) a plurality of arithmetic and logic processing units, each having one or two data inputs, wherein the inputs of each processing unit is operably coupled to read ports of said vector register file, and the output of these processing units are coupled to a write port of the vector register file; and    c) Plurality of accumulator registers, the input of which are operably coupled to the output of processing units, and wherein the output of the accumulator registers are operably coupled to a write port of the vector register file.    
     
     
         2 . The apparatus of  claim 1 , where LFSR leap-forward matrix is preformed or precalculated and stored for use in runtime. The values of this matrix are loaded into a plurality of vector registers and are used for LFSR leap-forward calculations.  
     
     
         3 . The apparatus of  claim 2 , where the matrix multiplication with a vector input data is performed using column-by-column conditional exclusive-OR operation which is accumulated over all the columns of the matrix using exclusive-OR accumulation of interim result with the vector accumulator. A given column of LFSR matrix is exclusive-OR'ed with the vector accumulator, only if the corresponding bit of the input data vector is one, and otherwise that column is skipped.  
     
     
         4 . The apparatus of  claim 3 , where a RISC processor is combined with a SIMD processor, whereby the RISC processor performs I/O processing and flow control for both itself and the SIMD processor, and one RISC and one SIMD instruction is executed every clock cycle.  
     
     
         5 . The apparatus of  claim 4 , wherein the value of N is selected from a group of values consisting of integer values between 4 and 256.  
     
     
         6 . The apparatus of  claim 5 , wherein each vector element is a byte.  
     
     
         7 . The apparatus of  claim 5 , wherein each vector element is a 16-bit fixed-point word.  
     
     
         8 . The apparatus of  claim 5 , wherein each vector element is a 32-bit fixed point word.  
     
     
         9 . The apparatus of  claim 5 , wherein each vector element is a floating-point value.