Long Instruction Word Controlling Plural Independent Processor Operations

Abstract

This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit ( 110 ) includes a multiplication unit ( 220 ) and an arithmetic logic unit ( 230 ). The data unit ( 110 ) may include a barrel rotator ( 235 ) for one input of the arithmetic logic unit ( 230 ). The rotated data may be stored in the first destination register instead of the multiply result. The address unit ( 120 ) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register ( 210 ). The status register ( 210 ) is set by a prior output of the arithmetic logic unit ( 230 ) and the instruction may specify some of the status bits protect from change. The address unit ( 120 ) preferably includes a plurality of base address registers ( 611 ), a full adder ( 615 ) and a left shifter ( 614 ). The full adder ( 615 ) may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder ( 615 ) output may update the base address register ( 611 ), either before supply of the address or following supply of the address. The index may be recalled from an index register ( 612 ) or an immediate value. In the preferred embodiment of this invention, the data unit ( 110 ) including the data registers ( 200 ), the multiplication unit ( 220 ) and the arithmetic logic unit ( 230 ), the address unit ( 120 ) and the instruction decode logic ( 250, 660 ) are embodied in at least one digital image/graphics processor ( 71, 72, 73, 74 ) as a part of a multiprocessor ( 100 ) formed in a single integrated circuit used in image processing.

1 - 117 . (canceled)  
   
   
       118 . A method of data processing comprising the steps of: 
 storing a plurality of data words of N bits in a memory by packing a plurality of data elements of L bits into each data word of N bits;    recalling a first data word of N bits from the memory;    recalling a second data word of N bits from the memory;    multiplying a first set of L bits of said first data word by a second set of L bits of said second data word, thereby obtaining a product having 2L bits, where N is greater than L;    left shifting said product by a selected number of bits, discarding said selected number of most significant bits of said product, thereby forming a shifted product;    forming a resultant data word of N bits having a third set of L bits corresponding to a most significant L bits of said shifted product and a fourth set of M bits, where said fourth set of M bits does not include a least significant set of L bits of said product, where N=L+M and M≧L; and    storing said resultant data word in the memory.    
   
   
       119 . The method of  claim 118 , further including: 
 storing a shift number in a predetermined data field in a special data register of a general purpose data register file.    
   
   
       120 . The method of  claim 118 , further comprising: 
 rounding said shifted product.    
   
   
       121 . The method of  claim 118 , wherein: 
 said fourth set of M bits of said resultant data word are derived from at least some bits of at least one of said first data word other than said first set of L bits and said second data word other than said second set of L bits.    
   
   
       122 . The method of  claim 121 , wherein: 
 said fourth set of M bits of said resultant data word consists of bits of said first data word other than said first set of L bits.    
   
   
       123 . The method of  claim 118 , wherein: 
 the memory includes a plurality of data registers;    said step of recalling said first data word comprises recalling said first data word from a first instruction specified one of said plurality of data registers;    said step of recalling said second data word comprises recalling said second data word from a second instruction specified one of said plurality of data registers; and    said step of storing said resultant data word in memory comprises storing said resultant data word in a third instruction specified one of said plurality of data registers.    
   
   
       124 . The method of  claim 118 , wherein: 
 said number of bits M is greater than said number of bits L.    
   
   
       125 . The method of  claim 118 , wherein: 
 said number of bits L equals 16 bits.    
   
   
       126 . The method of  claim 118 , wherein; 
 said number of bits L equals 8 bits.    
   
   
       127 . The method of  claim 118 , further comprising: 
 selectively rounding said shifted product if a predetermined rounding bit in a special purpose data register has a first state and not rounding said shifted product if said predetermined rounding bit has a second state different from said first state.    
   
   
       128 . The method of  claim 118 , further comprising: 
 selectively rounding said shifted product if a predetermined rounding bit in an instruction has a first state and not rounding said shifter product if said predetermined rounding bit has a second state different from said first state.    
   
   
       129 . The method of  claim 118 , wherein: 
 said step of left shifting said product further includes zero filling said selected number of least significant bits of said product.    
   
   
       130 . A method of data processing comprising the steps of: 
 storing a plurality of data words of N bits in a memory by packing a plurality of data elements of L bits into each data word of N bits;    recalling a first data word of N bits from the memory;    recalling a second data word of N bits from the memory;    multiplying a first set of L bits of said first data word by a second set of L bits of said second data word, thereby obtaining a product having 2L bits, where N is greater than L;    rounding L most significant bits of said product dependent on a L+1 most significant bit of said product, thereby forming a rounded product;    forming a resultant data word of N bits having a third set of L bits corresponding to a most significant L bits of said rounded product and a fourth set of M bits, where said fourth set of M bits does not include a least significant set of L bits of said product, where N=L+M and M≧L; and    storing said resultant data word in the memory.    
   
   
       131 . The method of  claim 130 , further comprising: 
 selectively rounding said product if a predetermined rounding bit in a special purpose data register has a first state and not rounding said product if said predetermined rounding bit has a second state different from said first state.    
   
   
       132 . The method of  claim 130 , further comprising: 
 selectively rounding said product if a predetermined rounding bit in an instruction has a first state and not rounding said product if said predetermined rounding bit has a second state different from said first state.    
   
   
       133 . The method of  claim 130 , wherein: 
 said fourth set of M bits of said resultant data word are derived from at least some bits of at least one of said first data word other than said first set of L bits and said second data word other than said second set of L bits.    
   
   
       134 . The method of  claim 133 , wherein: 
 said fourth set of M bits of said resultant data word consists of bits of said first data word other than said first set of L bits.    
   
   
       135 . The method of  claim 130 , wherein: 
 the memory includes a plurality of data registers;    said step of recalling said first data word comprises recalling said first data word from a first instruction specified one of said plurality of data registers;    said step of recalling said second data word comprises recalling said second data word from a second instruction specified one of said plurality of data registers; and    said step of storing said resultant data word in memory comprises storing said resultant data word in a third instruction specified one of said plurality of data registers.    
   
   
       136 . The method of  claim 130 , wherein: 
 said number of bits M is greater than said number of bits L.    
   
   
       137 . The method of  claim 130 , wherein: 
 said number of bits L equals 16 bits.    
   
   
       138 . The method of  claim 130 , wherein; 
 said number of bits L equals 8 bits.    
   
   
       139 . A method of data processing comprising the steps of: 
 storing a plurality of data words of N bits in a memory by packing a plurality of data elements of L bits into each data word of N bits;    recalling a first data word of N bits from the memory;    recalling a second data word of N bits from the memory;    multiplying a first set of L bits of said first data word by a second set of L bits of said second data word, thereby obtaining a product having 2L bits, where N is greater than L;    left shifting said product by a selected number of bits, discarding said selected number of most significant bits of said product, thereby forming a shifted product;    forming a resultant data word of N bits having a third set of L bits corresponding to a most significant L bits of said shifted product; and    storing said resultant data word in the memory.    
   
   
       140 . The method of  claim 139 , further including: 
 storing a shift number in a predetermined data field in a special data register of a general purpose data register file.    
   
   
       141 . The method of  claim 139 , further comprising: 
 rounding said shifted product.    
   
   
       142 . The method of  claim 139 , further comprising: 
 selectively rounding said product if a predetermined rounding bit in a special purpose data register has a first state and not rounding said product if said predetermined rounding bit has a second state different from said first state.    
   
   
       143 . The method of  claim 139 , further comprising: 
 selectively rounding said product if a predetermined rounding bit in an instruction has a first state and not rounding said product if said predetermined rounding bit has a second state different from said first state.    
   
   
       144 . The method of  claim 139 , wherein: 
 the memory includes a plurality of data registers;    said step of recalling said first data word comprises recalling said first data word from a first instruction specified one of said plurality of data registers;    said step of recalling said second data word comprises recalling said second data word from a second instruction specified one of said plurality of data registers; and    said step of storing said resultant data word in memory comprises storing said resultant data word in a third instruction specified one of said plurality of data registers.    
   
   
       145 . The method of  claim 139 , wherein: 
 said number of bits L equals 16 bits.    
   
   
       146 . The method of  claim 139 , wherein; 
 said number of bits L equals 8 bits.    
   
   
       147 . The method of  claim 139 , wherein: 
 said step of left shifting said product further includes zero filling said selected number of least significant bits of said product.    
   
   
       148 . A method of data processing comprising the steps of: 
 storing a plurality of data words of N bits in a memory by packing a plurality of data elements of L bits into each data word of N bits;    recalling a first data word of N bits from the memory;    recalling a second data word of N bits from the memory;    multiplying the N/2 most significant bits of said first data word by the N/2 most significant bits of said second data word, thereby obtaining a first product of 2N bits;    multiplying the N/2 least significant bits of said first data word by the N/2 least significant bits of said second data word, thereby obtaining a second product of 2N bits;    shifting said first product by a selected number of bits;    shifting said second product by said selected number of bits; and    forming a resultant data word of N bits having N/2 most significant bits corresponding to a most significant N/2 bits of said shifted first product and N/2 least significant bits corresponding to a most significant N/2 bits of said shifted second product; and    storing said resultant data word in the memory.    
   
   
       149 . The method of  claim 148 , further including: 
 storing a shift number in a predetermined data field in a special data register of a general purpose data register file.    
   
   
       150 . The method of  claim 148 , further comprising: 
 rounding said shifted first product, whereby said N/2 most significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted first product; and    rounding said shifted second product, whereby said N/2 least significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted second product.    
   
   
       151 . The method of  claim 148 , further comprising: 
 selectively rounding said shifted first product if a predetermined rounding bit in a special purpose data register has a first state, whereby said N/2 most significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted first product, and not rounding said shifted first product if said predetermined rounding bit has a second state different from said first state; and    selectively rounding said shifted second product if said predetermined rounding bit in said special purpose data register has said first state, whereby said N/2 least significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted second product, and not rounding said shifted second product if said predetermined rounding bit has said second state.    
   
   
       152 . The method of  claim 148 , further comprising: 
 selectively rounding said shifted first product if a predetermined rounding bit in an instruction has a first state, whereby said N/2 most significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted first product, and not rounding said shifted first product if said predetermined rounding bit has a second state different from said first state; and    selectively rounding said shifted second product if said predetermined rounding bit in said instruction has said first state, whereby said N/2 least significant bits of said resultant data word consist of said N/2 most significant bits of said rounded shifted second product, and not rounding said shifted second product if said predetermined rounding bit has said second state.    
   
   
       153 . The method of  claim 148 , further comprising: 
 the memory includes a plurality of data registers;    said step of recalling said first data word of N bits from memory comprises recalling said first data word from a first instruction specified one of a plurality of data registers;    said step of recalling said second data word of N bits from memory comprises recalling said second data word from a second instruction specified one of said plurality of data registers; and    said step of storing said resultant data word in memory comprises storing said resultant data word in a third instruction specified one of said plurality of data registers.    
   
   
       154 . A method of data processing comprising the steps of: 
 storing a plurality of data words of N bits in a memory by packing a plurality of data elements of L bits into each data word of N bits;    recalling a first data word of N bits from the memory;    recalling a second data word of N bits from the memory;    multiplying the N/2 most significant bits of said first data word by the N/2 least significant bits of said second data word, thereby obtaining a first product of 2N bits;    multiplying the N/2 least significant bits of said first data word by the N/2 least significant bits of said second data word, thereby obtaining a second product of 2N bits;    rounding said first product;    rounding said second product;    forming a resultant data word of N bits having N/2 most significant bits corresponding to a most significant N/2 bits of said rounded first product and N/2 least significant bits corresponding to a most significant N/2 bits of said rounded second product; and    storing said resultant data word in the memory.    
   
   
       155 . The method of  claim 154 , wherein: 
 said step of rounding said first product includes selectively rounding said first product if a predetermined rounding bit in a special purpose data register has a first state, whereby said N/2 most significant bits of said resultant data word consist of said N/2 most significant bits of said rounded first product, and not rounding said first product if said predetermined rounding bit has a second state different from said first state; and    said step of rounding said second product includes selectively rounding said second product if said predetermined rounding bit in said special purpose data register has said first state, whereby said N/2 least significant bits of said resultant data word consist of said N/2 most significant bits of said rounded second product, and not rounding said second product if said predetermined rounding bit has said second state.    
   
   
       156 . The method of  claim 154 , further comprising: 
 said step of rounding said first product includes selectively rounding said first product if a predetermined rounding bit in an instruction has a first state, whereby said N/2 most significant bits of said resultant data word consist of said N/2 most significant bits of said rounded first product, and not rounding said first product if said predetermined rounding bit has a second state different from said first state; and    said step of rounding said second product includes selectively rounding said second product if said predetermined rounding bit in said instruction has said first state, whereby said N/2 least significant bits of said resultant data word consist of said N/2 most significant bits of said rounded second product, and not rounding said second product if said predetermined rounding bit has said second state.    
   
   
       157 . The method of  claim 154 , wherein: 
 the memory includes a plurality of data registers;    said step of recalling said first data word of N bits from memory comprises recalling said first data word from a first instruction specified one of a plurality of data registers;    said step of recalling said second data word of N bits from memory comprises recalling said second data word from a second instruction specified one of said plurality of data registers; and    said step of storing said resultant data word in memory comprises storing said resultant data word in a third instruction specified one of said plurality of data registers.