Video processing architecture definition by function graph methodology

Abstract

A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

1 - 20 . (canceled)  
   
   
       21 . A method for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;    generating a hardware architecture design for a video processing application;    comparing the hardware architecture design to the function graph to determine if the design complies with the function graph; and    in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation,    wherein the specification is the AVC standard.    
   
   
       22 . A method for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;    generating a hardware architecture design for a video processing application;    comparing the hardware architecture design to the function graph to determine if the design complies with the function graph; and    in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation,    wherein said functions include at least one of front-end blocks, compression-loop blocks, and control functions.    
   
   
       23 . The method of  claim 22  wherein said front-end blocks include motion related functions, including at least one of: vector search functions, vector-based prediction functions, pre-coding decision functions, macroblock level de-interlace functions, and filter functions.  
   
   
       24 . The method of  claim 22  wherein said compression-loop blocks include compression functions, including at least one of: universal variable length decode/encode for video stream element functions, CABAC encoder and decoder functions, reconstruction functions (including de-quantization, IDCT, and de-compensation), and transform loop functions (including de/compensation, I/DCT, de/quantization and post-quantization processing).  
   
   
       25 . The method of  claim 22  wherein said control functions include at least one of: pre-decode slide functions, pre-decode macro-block functions, sequence controls, pre-encode macro-block functions, macro-block encoding control functions, and post-coding decision functions.  
   
   
       26 . A method for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;    generating a hardware architecture design for a video processing application;    comparing the hardware architecture design to the function graph to determine if the design complies with the function graph; and    in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation,    wherein said control information includes at least one of macro-block control information, and upper level control information.    
   
   
       27 . The method of  claim 26  wherein said macro-block control information includes at least one of motion related control and compression loop control.  
   
   
       28 . The method of  claim 26  wherein said upper level control information includes at least one of sequence preparation information and picture processing information.  
   
   
       29 . A method for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;    generating a hardware architecture design for a video processing application;    comparing the hardware architecture design to the function graph to determine if the design complies with the function graph; and    in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation,    wherein generating a function graph that graphically represents criteria of the specification includes accessing one or more electronic libraries that store external sources/targets, functional nodes, data elements, inter-node communication, and control information components reflected in the specification, and    wherein said functional nodes stored in the functional node library include at least one of: front-end blocks, compression-loop blocks, and control functions.    
   
   
       30 . The method of  claim 29  wherein said front-end blocks include motion related functions, including at least one of: vector search functions, vector-based prediction functions, pre-coding decision functions, macro-block level de-interlace functions, and filter functions.  
   
   
       31 . The method of  claim 29  wherein said compression-loop blocks include compression functions, including at least one of: universal variable length decode/encode for video stream element functions, CABAC encoder and decoder functions, reconstruction functions including de-quantization, IDCT, and de-compensation, and transform loop functions including de/compensation, I/DCT, de/quantization and post-quantization processing.  
   
   
       32 . The method of  claim 29  wherein said control functions include at least one of: pre-decode slice functions, pre-decode macro-block functions, sequence controls, pre-encode macro-block functions, macro-block encoding control functions, and post-coding decision functions.  
   
   
       33 . A method for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;    generating a hardware architecture design for a video processing application;    comparing the hardware architecture design to the function graph to determine if the design complies with the function graph; and    in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation,    wherein generating a function graph that graphically represents criteria of the specification includes accessing one or more electronic libraries that store external sources/targets, functional nodes, data elements, inter-node communication, and control information components reflected in the specification, and    wherein inter-node communication stored in the inter-node-communication library includes inter-node communication between at least one of: (a) an external source and a motion engine, (b) an external source and other front-end processing blocks, (c) front-end processing blocks, (d) front-end compression loops, (d) compression-loop blocks, and (e) a compression-loop and an external source.    
   
   
       34 . A system for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or internode-communication;    a hardware architecture design module for generating a hardware architecture design for a video processing application; and    an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation    wherein the specification is the AVC standard.    
   
   
       35 . A system for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or internode-communication;    a hardware architecture design module for generating a hardware architecture design for a video processing application; and    an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation,    wherein said functions include at least one of front-end blocks, compression-loop blocks, and control functions.    
   
   
       36 . The system of  claim 35  wherein said front-end blocks include motion related functions, including at least one of: vector search functions, vector-based prediction functions, pre-coding decision functions, macroblock level de-interlace functions, and filter functions.  
   
   
       37 . The system of  claim 35  wherein said compression-loop blocks include compression functions, including at least one of: universal variable length decode/encode for video stream element functions, CABAC encoder and decoder functions, reconstruction functions (including de-quantization, IDCT, and de-compensation), and transform loop functions (including de/compensation, I/DCT, de/quantization and post-quantization processing).  
   
   
       38 . The system of  claim 35  wherein said control functions include at least one of: pre-decode slide functions, pre-decode macro-block functions, sequence controls, pre-encode macro-block functions, macro-block encoding control functions, and post-coding decision functions.  
   
   
       39 . A system for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or internode-communication;    a hardware architecture design module for generating a hardware architecture design for a video processing application; and    an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation,    wherein said control information includes at least one of macro-block control information, and upper level control information.    
   
   
       40 . The system of  claim 39  wherein said macro-block control information includes at least one of motion related control and compression loop control.  
   
   
       41 . The system of  claim 39  wherein said upper level control information includes at least one of sequence preparation information and picture processing information.  
   
   
       42 . A system for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or internode-communication;    a hardware architecture design module for generating a hardware architecture design for a video processing application; and    an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation,    wherein the function graph module is further configured to access one or more electronic libraries that store external sources/targets, functional nodes, data elements, inter-node communication, and control information components reflected in the specification, and    wherein said functional nodes stored in the functional node library include at least one of: front-end blocks, compression-loop blocks, and control functions.    
   
   
       43 . The system of  claim 42  wherein said front-end blocks include motion related functions, including at least one of: vector search functions, vector-based prediction functions, pre-coding decision functions, macro-block level de-interlace functions, and filter functions.  
   
   
       44 . The system of  claim 42  wherein said compression-loop blocks include compression functions, including at least one of: universal variable length decode/encode for video stream element functions, CABAC encoder and decoder functions, reconstruction functions including de-quantization, IDCT, and de-compensation, and transform loop functions including de/compensation, I/DCT, de/quantization and post-quantization processing.  
   
   
       45 . The system of  claim 42  wherein said control functions include at least one of: pre-decode slice functions, pre-decode macro-block functions, sequence controls, pre-encode macro-block functions, macro-block encoding control functions, and post-coding decision functions.  
   
   
       46 . A system for designing video processing architecture in accordance with a video processing a particular specification, comprising: 
 a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or internode-communication;    a hardware architecture design module for generating a hardware architecture design for a video processing application; and    an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation,    wherein the function graph module is further configured to access one or more electronic libraries that store external sources/targets, functional nodes, data elements, inter-node communication, and control information components reflected in the specification, and    wherein inter-node communication stored in the inter-node-communication library includes inter-node communication between at least one of: (a) an external source and a motion engine, (b) an external source and other front-end processing blocks, (c) front-end processing blocks, (d) front-end compression loops, (d) compression-loop blocks, and (e) a compression-loop and an external source.