Saving/Restoring Task State Data From/To Device Controller Host Interface Upon Command From Host Processor To Handle Task Interruptions

Abstract

A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

1 . A system that performs a save/restore procedure in an electronic device, 
 the system interrupting a first task after the system receives a first signal indicating an interruption by a second task during a period in which the system performs the first task,    the system saving first information indicating a status of the first task at a time the first task is interrupted by the second task,    the system restarting the first task after the second task is completed,    the system interrupting a third task after the system receives a second signal indicating an interruption by a fourth task during a period in which the system performs the third task,    the system saving second information indicating a status of the third task at a time the third task is interrupted by the fourth task, and    the system restarting the third task after the fourth task is completed.    
   
   
       2 . The system according to  claim 1 , 
 the system saving the first information in a first register, and    the system saving the second information in a second register different from the first register.    
   
   
       3 . The system according to  claim 1 , 
 the system saving the first information in a first region of a memory included in the system, and    the system saving the second information in a second region of the memory different from the first region.    
   
   
       4 . The system according to  claim 1 , 
 the first information including at least one of a register value, an address, a counter value, and an internal value.    
   
   
       5 . The system according to  claim 1 , 
 the first information including third information obtained by the system for performing the first task.    
   
   
       6 . The system according to  claim 2 , comprising: 
 a host interface that reads out the first information from the first register after the second task is completed.    
   
   
       7 . The system according to  claim 6 , 
 the system restarting the first task after the host interface reads out the first information from the first register.    
   
   
       8 . The system according to  claim 1 , 
 the second task having a priority higher than the first task, and    the fourth task having a priority higher than the third task.    
   
   
       9 . A CPU, 
 the CPU interrupting a first task after a system receives a first signal indicating an interruption by a second task during a period in which the CPU performs the first task,    the CPU restarting the first task after the CPU refers to first information indicating a status of the first task at a time the first task is interrupted by the second task,    the CPU interrupting a second task after the system receives a second signal indicating an interruption by a fourth task during a period in which the CPU performs the third task, and    the CPU restarting the third task after the CPU refers to second information indicating a status of the third task at a time the third task is interrupted by the fourth task.    
   
   
       10 . The CPU according to  claim 9 , wherein the CPU refers to 
 the first information saved in a first register, and    the second information saved in a second register different from the first register.    
   
   
       11 . A CPU, 
 the CPU interrupting a first task after a system receives a first signal indicating an interruption by a second task during a period in which the CPU performs the first task,    the CPU restarting the first task after the CPU receives first information indicating a status of the first task at a time the first task is interrupted by the second task,    the CPU interrupting a second task after the system receives a second signal indicating an interruption by a fourth task during a period in which the CPU performs the third task, and    the CPU restarting the third task after the CPU receives second information indicating a status of the third task at a time the third task is interrupted by the fourth task.    
   
   
       12 . A electronic device, comprising: 
 a CPU; and    a display,    the CPU interrupting a first task after a system receives a first signal indicating an interruption by a second task during a period in which the CPU performs the first task,    the CPU restarting the first task after the CPU receives first information indicating a status of the first task at a time the first task is interrupted by the second task,    the CPU interrupting a second task after the system receives a second signal indicating an interruption by a fourth task during a period in which the CPU performs the third task, and    the CPU restarting the third task after the CPU receives second information indicating a status of the third task at a time the third task is interrupted by the fourth task,    the display displaying results the first task, the second task, the third task, and the fourth task.    
   
   
       13 . A controller, comprising: 
 a first register that saves first information indicating a status of a first task at a time the first task is interrupted by a second task;    a second register that saves second information indicating a status of a third task at a time the third task is interrupted by a fourth task,    wherein the first task is interrupted by a CPU after a system receives a first signal indicating an interruption by the second task during a period in which the CPU performs the first task,    the first task being restarted by the CPU after the CPU refers to the first information,    the third task being interrupted by the CPU after a system receives a second signal indicating an interruption by the fourth task during a period in which the CPU performs the third task,    the third task being restarted by the CPU after the CPU refers to the second information.    
   
   
       14 . A controller, comprising: 
 a first register that saves first information indicating a status of a first task at a time the first task is interrupted by a second task;    a second register that saves second information indicating a status of a third task at a time the third task is interrupted by a fourth task,    wherein the first task is interrupted by a CPU after a system receives a first signal indicating an interruption by the second task during a period in which the CPU performs the first task,    the first information being referred to by the CPU after the second task is completed,    the first task being restarted by the CPU after the CPU refers to the first information,    wherein the third task is interrupted by the CPU after a system receives a second signal indicating an interruption by the fourth task during a period in which the CPU performs the third task,    the second information being referred to by the CPU after the fourth task is completed,    the third task being restarted by the CPU after the CPU refers to the second information.