Memory device

Abstract

A memory device is provided which includes a substrate, lower electrodes, selecting elements, memory elements formed of chalcogenide material and upper electrodes. The selecting elements and the memory elements are arranged to be disposed between the upper electrodes and the lower electrodes. In addition, the lower electrodes, the memory elements and the upper electrodes are disposed along lines perpendicular to the substrate surface when the memory device is viewed in a first direction.

1 . A memory device comprising: 
 a substrate;    a plurality of lower electrodes;    a plurality of selecting elements;    a plurality of memory elements, each formed of chalcogenide material; and    a plurality of upper electrodes,    wherein said selecting elements and said memory elements are respectively disposed between said lower electrodes and said upper electrodes and wherein said lower elements, said memory elements and said upper electrodes are disposed along lines perpendicular to a surface of the substrate when said memory device is viewed in a first direction.    
     
     
         2 . A memory device according to  claim 1 , wherein said lower electrodes, said memory elements and said upper electrodes are disposed along lines perpendicular to the substrate surface when the memory device is viewed in a second direction which is perpendicular to the first direction.  
     
     
         3 . A memory device according to  claim 1 , wherein each of said memory elements has a substantially square shape when viewed in said first direction.  
     
     
         4 . A memory device according to  claim 2 , wherein each of said memory elements has a substantially square shape when viewed in said first direction.  
     
     
         5 . A memory device according to  claim 1 , wherein said selecting elements are respectively formed on said lower electrodes and wherein said memory elements are respectively formed on said selecting elements.  
     
     
         6 . A memory device according to  claim 2 , wherein said selecting elements are respectively formed on said lower electrodes and wherein said memory elements are respectively formed on said selecting elements.