Manufacturing method of flash memory

Abstract

A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned through the oxide layer into blocks. The oxide layer is removed and an inter-gate dielectric layer is formed in the opening. A control gate that completely fills the opening is formed. A cap layer is formed over the control gate. The mask layer is then removed. Using the cap layer as a mask, a portion of the conductive layer is removed to form two floating gates under the control gate. An insulating layer is formed on the substrate. Source/drain regions are formed in the substrate on the respective sides of the control gate.

1 . A method of fabricating flash memory, comprising: 
 providing a substrate;    forming a first dielectric layer, a first conductive layer and a mask layer sequentially on the substrate, wherein the material constituting the first conductive layer at least comprises doped polysilicon;    patterning the mask layer to form an opening that exposes a portion of the first conductive layer;    performing a thermal oxidation process to form an oxide layer on the exposed first conductive layer;    removing the oxide layer to expose the substrate;    forming a second dielectric layer in the opening;    forming a second conductive layer on the substrate to fill the opening completely;    removing the mask layer and a portion of the first conductive layer under the mask layer to expose a portion of the substrate so that a pair of third conductive layers is formed under the second conductive layer;    forming an insulating layer on the substrate; and    forming source/drain regions in the substrate on respective sides of the second conductive layer.    
   
   
       2 . The method of  claim 1 , further comprising forming a doped region in the substrate between the two third conductive layers.  
   
   
       3 . The method of  claim 2 , wherein the doped region is formed in the substrate exposed by the first conductive layer after the step of removing the oxide layer.  
   
   
       4 . The method of  claim 1 , wherein the step for removing the mask layer and a portion of the first conductive layer underneath the mask layer to expose a portion of the substrate and forming the two third conductive layers comprises: 
 performing an oxidation process to form a cap layer on the surface of the second conductive layer;    removing the mask layer to expose a portion of the first conductive layer; and    removing a portion of the first conductive layer using the cap layer as a mask so that two third conductive layers are formed underneath the second conductive layer.    
   
   
       5 . The method of  claim 4 , wherein the step of forming a cap layer over the second conductive layer comprises performing an oxidation process.  
   
   
       6 . The method of  claim 1 , wherein the second conductive layer serves as a control gate.  
   
   
       7 . The method of  claim 1 , wherein the material constituting the second conductive layer comprises doped polysilicon.  
   
   
       8 . The method of  claim 1 , wherein the two third conductive layers serve as floating gates.  
   
   
       9 . The method of  claim 1 , wherein the step of removing the oxide layer comprises performing an etching operation by using hydrofluoric acid as an etching agent.  
   
   
       10 . The method of  claim 1 , wherein the material constituting the mask layer comprises silicon nitride.  
   
   
       11 . The method of  claim 1 , wherein the second dielectric layer comprises an oxide/nitride/oxide composite stacked layer.  
   
   
       12 . The method of  claim 1 , wherein the material constituting the first dielectric layer comprises silicon oxide.  
   
   
       13 . The method of  claim 1 , wherein the junction between the oxide layer and the first conductive layer has the shape of an arc.  
   
   
       14 . The method of  claim 1 , after the step of removing the oxide layer to expose the substrate, further comprising patterning the first conductive layer to dissect the first conductive layer into blocks.  
   
   
       15 . A method for fabricating flash memory, comprising: 
 providing a substrate;    forming a first dielectric layer, a first conductive layer and a first mask layer sequentially over the substrate, wherein the material constituting the first conductive layer at least comprises doped polysilicon;    patterning the first mask layer, the first conductive layer, the first dielectric layer and the substrate to form a plurality of trenches in the substrate;    depositing insulating material to fill the trenches and form an array of device isolation structures for defining a plurality of parallel-arranged first active regions extending in a first direction and a plurality of parallel-arranged second active regions extending in a second direction, wherein the first direction and the second direction cross over each other;    forming a plurality of doped regions in the substrate within the first active regions;    patterning the first mask layer to form a plurality of openings, wherein the openings exposes at least a portion of the first conductive layer on the first active regions;    performing a thermal oxidation process to form an oxide layer on the exposed first conductive layer;    removing the oxide layer to expose the substrate;    patterning the first conductive layer to dissect the first conductive layer into blocks;    forming a second dielectric layer in the openings;    forming a second conductive layer that fills the openings on the substrate to serve as control gates;    performing a thermal oxidation process to form a cap layer on the second conductive layers;    removing the first mask layer to expose a portion of the first conductive layer;    removing a portion of the first conductive layer by using the cap layers as a mask to form a plurality of floating gates under the second conductive layers wherein every two floating gates are formed in every first active region defined by four device isolation structures with the doped region, and the doped region are formed between the two floating gates,    forming an insulating layer over the substrate;    forming source/drains region in the substrate on the respective sides of the second conductive layer; and    forming a plurality of conductive plugs over the substrate to connect electrically with corresponding source/drain regions.    
   
   
       16 . The method of  claim 15 , after forming the device isolation structure, further comprising forming a second mask layer over the substrate.  
   
   
       17 . The method of  claim 15 , wherein the doped regions are formed in the substrate exposed by the first conductive layer after removing the oxide layer.  
   
   
       18 . The method of  claim 15 , wherein the second dielectric layer comprises an oxide/nitride/oxide composite stacked layer.  
   
   
       19 . The method of  claim 15 , wherein the material constituting the first dielectric layer comprises silicon oxide.  
   
   
       20 . The method of  claim 15 , wherein the material constituting the second conductive layer comprises doped polysilicon.  
   
   
       21 . The method of  claim 15 , wherein the step of removing the oxide layer comprises performing an etching operation using hydrofluoric acid as an etching agent.  
   
   
       22 . The method of  claim 15 , wherein the junction between the oxide layer and the first conductive layer has the shape of an arc.