Semiconductor device and method of manufacturing same

Abstract

A semiconductor device comprising: a transistor region formed on a semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors; a diffused layer formed on the surface of said semiconductor substrate between the adjacent first and a second select transistors of said memory cell arrays in said transistor region; a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors adjacent to each other; a second sidewall film formed on said first sidewall film; and a conducting layer formed between said first and second select transistors, so as to contact with said diffused layer, wherein the edge of a contact portion is positioned at a distance no less than the thickness of said second sidewall film from the sidewalls of said first and second select transistors.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a transistor region formed on said semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors;    a diffused layer formed on the surface of said semiconductor substrate between the adjacent first and a second select transistors of said memory cell arrays in said transistor region;    a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors adjacent to each other;    a second sidewall film formed on said first sidewall film; and    a conducting layer formed between said first and second select transistors, so as to contact with said diffused layer, wherein the edge of a contact portion is positioned at a distance no less than the thickness of said second sidewall film from the sidewalls of said first and second select transistors.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the thickness of said second sidewall film is greater than the thickness of said first sidewall film.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein said first sidewall film is a silicon dioxide film and said second sidewall film is a silicon nitride film.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein said diffused layer has a first impurity-diffused layer region and a second impurity-diffused layer region formed in the center thereof and having an impurity concentration higher than that of said first impurity-diffused layer region.  
   
   
       5 . The semiconductor device according to  claim 4 , wherein said conducting layer contacts with said second impurity-diffused layer region.  
   
   
       6 . The semiconductor device according to  claim 1 , wherein said second sidewall film is formed so as to cover at least part of the top surface and the side surface of said first sidewall film, wherein the edge of said contact portion is positioned at a distance no less than the total thickness of said first and second sidewall films from the sidewalls of said first and second select transistors.  
   
   
       7 . The semiconductor device according to  claim 6 , wherein the height of said second sidewall film is greater than the sum of the thicknesses of said first sidewall film and said second sidewall film.  
   
   
       8 . The semiconductor device according to  claim 6 , wherein said diffused layer has a first impurity-diffused layer region and a second impurity-diffused layer region formed in the center thereof and having an impurity concentration higher than that of said first impurity-diffused layer region.  
   
   
       9 . The semiconductor device according to  claim 8 , wherein said conducting layer contacts with said second impurity-diffused layer region.  
   
   
       10 . The semiconductor device according to  claim 6 , wherein said first sidewall film and said second sidewall film are silicon nitride films.  
   
   
       11 . A method of manufacturing a semiconductor device comprising: 
 forming on a semiconductor substrate a plurality of memory cell arrays having a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors;    forming a first diffused layer on the surface of said semiconductor substrate between said memory cell transistors, between said memory cell transistors and said select transistors and between said select transistors disposed at the ends of said memory cell arrays adjacent to each other;    forming a first insulating film so as to fill spaces between said memory cell transistors, between said memory cell transistors and said select transistors and between said select transistors disposed at the ends of said memory cell arrays adjacent to each other;    removing said first insulating film so that sidewall films having a first predetermined value of film thickness are formed between said select transistors on the sidewall thereof;    forming a second diffused layer on the surface of said semiconductor substrate between said select transistors using said sidewall films as masks;    removing said sidewall films;    forming a second insulating film for covering the side and bottom surfaces of an area between said select transistors;    forming third insulating films on the lateral sides of said second insulating film so that the total thickness of said third insulating film and said second insulating film amounts to a second predetermined value equal to or greater than said first predetermined value;    forming a fourth insulating film so as to fill a space between said third insulating films;    creating an opening between said select transistors whereby the top surface of said second diffused layer is exposed; and    burying a conductive material in said opening to form a contact portion.    
   
   
       12 . The method of manufacturing a semiconductor device according to  claim 11 , wherein said third insulating films are also formed on the lateral sides and on the base of said second insulating film.  
   
   
       13 . The method of manufacturing a semiconductor device according to  claim 12 , wherein said opening is formed by etching said fourth insulating film on the condition that said fourth insulating film has a higher selection ratio than said third insulating films so that the top surface of the base of said third insulating films is exposed and by etching said third and second insulating films on the condition that said third insulating films have a higher selection ratio than said fourth insulating film so that the top surface of said second diffused layer is exposed.  
   
   
       14 . The method of manufacturing a semiconductor device according to  claim 12 , wherein said second and third insulating films are silicon nitride films and said fourth insulating film is a silicon dioxide film.  
   
   
       15 . The method of manufacturing a semiconductor device according to  claim 11 , further including, between forming said second insulating film and forming said third insulating film, forming a fifth insulating film on said second insulating film so as to fill a space between said select transistors up to a predetermined height and forming said third insulating film on the lateral sides of said second insulating film and on said fifth insulating film.  
   
   
       16 . The method of manufacturing a semiconductor device according to  claim 15 , wherein said opening is formed by etching said fourth insulating film on the condition that said fourth insulating film has a higher selection ratio than said third insulating films so that the top surface of the base of said third insulating films is exposed, by etching said third insulating film on the condition that said third insulating film has a higher selection ratio than said fourth insulating film so that the top surface of said fifth insulating film is exposed, by etching said fifth insulating film on the condition that said fifth insulating film has a higher selection ratio than said third insulating film so that the top surface of the base of said second insulating film is exposed, and by etching said second insulating film on the condition that said second insulating film has a higher selection ratio than said fifth insulating film so that the top surface of said second diffused layer is exposed.  
   
   
       17 . The method of manufacturing a semiconductor device according to  claim 15 , wherein said second and third insulating films are silicon nitride films and said fourth and fifth insulating films are silicon dioxide films.  
   
   
       18 . A method of manufacturing a semiconductor device comprising: 
 forming on a semiconductor substrate a plurality of memory cell arrays having a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors;    forming a first diffused layer on the surface of said semiconductor substrate between said memory cell transistors, between said memory cell transistors and said select transistors and between said select transistors disposed at the ends of said memory cell arrays adjacent to each other;    forming a first insulating film so as to fill spaces between said memory cell transistors, between said memory cell transistors and said select transistors and between said select transistors disposed at the ends of said memory cell arrays adjacent to each other;    removing said first insulating film so that sidewall films having a first predetermined value of film thickness are formed between said select transistors on the sidewall thereof;    forming a second diffused layer on the surface of said semiconductor substrate between said select transistors using said sidewall films as masks;    forming a second insulating film so as to fill a space between said sidewall films;    removing said sidewall films and said second insulating film so that the predetermined heights thereof are reached;    forming a third insulating film having a second predetermined value of film thickness equal to or greater than said first predetermined value by covering the side surface and bottom surface of an area between said select transistors;    forming a fourth insulating film on said third insulating film so as to fill a space between said select transistors;    creating an opening between said select transistors whereby the top surface of said second diffused layer is exposed; and    burying a conductive material in said opening to form a contact portion.    
   
   
       19 . The method of manufacturing a semiconductor device according to  claim 18 , wherein said opening is formed by etching said fourth insulating film on the condition that said fourth insulating film has a higher selection ratio than said third insulating films so that the top surface of the base of said third insulating films is exposed, by etching said third insulating film on the condition that said third insulating film has a higher selection ratio than said fourth insulating film so that the top surface of said second insulating film is exposed, and by etching said second insulating film on the condition that said second insulating film has a higher selection ratio than said third insulating film so that the top surface of said second diffused layer is exposed.  
   
   
       20 . The method of manufacturing a semiconductor device according to  claim 18 , wherein said first, second and third insulating films are silicon dioxide films and said third insulating film is a silicon nitride film.