Continuously Referencing Signals over Multiple Layers in Laminate Packages

Abstract

A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

1 . A laminate chip package, comprising:
 a plurality of insulator layers; and   a plurality of patterned conductive layers comprising a first layer, a fourth layer, and two intermediate layers between successive insulator layers,   wherein selective portions are connected between layers using vias that extend through the successive insulator layers, wherein a first area of the first layer under a first chip is connected to a source voltage and wherein a second area of the first layer under a second chip is connected to a ground potential;   a conductive signal plane positioned in a conductive layer within the plurality of conductive layers, and extending from beneath the first chip to beneath the second chip, wherein the signal plane maintains a relatively consistent impedance from beneath the first chip to beneath the second chip by a balanced proximity of a second conductive layer connected to the source voltage and the fourth conductive layer connected to the ground potential, without adding layers to the laminate chip package.   
     
     
         2 . The laminate chip package of  claim 1 , wherein a source voltage plane is connected from the first layer in the first area to one of the two intermediate layers in the second area using one or more vias. 
     
     
         3 . The laminate chip package of  claim 2 , wherein the conductive signal plane is connected from a second layer within two intermediate layers in the first area to a third layer within the two intermediate layers in the second area using one or more vias. 
     
     
         4 . The laminate chip package of  claim 3 , wherein a ground plane is connected from the third layer in the first area to the fourth layer in the second area using one or more vias such that the signal plane maintains a balanced proximity to the source voltage plane and the ground plane. 
     
     
         5 . The laminate chip package of  claim 1 , wherein the chip is a first chip and wherein a third area of the top layer under a second chip is connected to a source voltage;
 wherein the conductive signal plane is positioned within the plurality of conductive layers such that a path of the conductive signal plane maintains a relatively consistent impedance from beneath the second area to beneath the third area by a balanced proximity of a conductive layer connected to the source voltage and a conductive layer connected to the ground potential.   
     
     
         6 . A method of fabricating a laminate chip package, comprising:
 receiving a laminate package design for a laminate chip package having a plurality of insulator layers and a plurality of patterned conductive layers comprising a first conductive layer, a fourth conductive layer, and two intermediate conductive layers;   identifying a first preferred voltage plane for the first conductive layer within a first area of the laminate package design;   identifying a second preferred voltage plane for the first conductive layer within a second area of the laminate package design, wherein the first preferred voltage plane is one of a source voltage plane or a ground plane and the second preferred voltage plane is the other of the source voltage plane and the ground plane;   positioning signal planes, source voltage planes, and ground planes within the plurality of conductive layers such that a path of the signal plane maintains a relatively consistent impedance from beneath the first area to beneath the second area by a balanced proximity to a conductive layer connected to the source voltage and a conductive layer connected to ground potential, without adding layers to the laminate package design, to form a mixed voltage plane package design; and   fabricating the laminate chip package based on the mixed voltage plane package design.   
     
     
         7 . The method of  claim 6 , wherein the first area is under a first chip and wherein the first voltage plane is a source voltage plane. 
     
     
         8 . The method of  claim 7 , wherein the second area is not under a chip and wherein the second preferred voltage plane is the ground plane. 
     
     
         9 . The method of  claim 8 , further comprising:
 identifying a third preferred voltage plane for the first conductive layer within a third area of the laminate package design under a second chip, wherein the third preferred voltage plane is the source voltage plane,   wherein the positioning step includes positioning the signal planes, the source voltage planes, and the ground planes within the plurality of conductive layers such that a path of the signal plane maintains a relatively consistent impedance from beneath the second area to beneath the third area by a balanced proximity of a conductive layer connected to the source voltage and a conductive layer connected to ground potential, without adding layers to the laminate package design.   
     
     
         10 . The method of  claim 6 , wherein the positioning step comprises connecting a source voltage plane from the first layer in the first area to a second layer within the two intermediate layers in the second area using one or more vias. 
     
     
         11 . The method of  claim 10 , wherein the positioning step comprises connecting the signal plane from a second layer within the two intermediate layers in the first area to a third layer within the two intermediate layers in the second area using one or more vias. 
     
     
         12 . The method of  claim 11 , wherein the positioning step comprises connecting a ground plane from the third layer within the two intermediate layers in the first area to the fourth layer in the second area using one or more vias such that the signal plane maintains a balanced proximity to the source voltage plane and the ground plane. 
     
     
         13 . A system for fabricating a laminate chip package, comprising:
 a package design system that provides a laminate package design for a laminate chip package having a plurality of insulator layers and a plurality of patterned conductive layers comprising a first conductive layer, a fourth conductive layer, and two intermediate conductive layers;   a design analysis engine that identifies a first preferred voltage plane for the first conductive layer within a first area of the laminate package design and a second preferred voltage plane for the first conductive layer within a second area of the laminate package design, wherein the first preferred voltage plane is one of a source voltage plane or a ground plane and the second preferred voltage plane is the other of the source voltage plane and the ground plane;   a reference plane adjustment engine that positions signal planes, source voltage planes, and ground planes within the plurality of conductive layers such that a path of the signal plane maintains a relatively consistent impedance from beneath the first area to beneath the second area by a balanced proximity to a conductive layer connected to the source voltage and a conductive layer connected to ground potential, without adding layers to the laminate package design, to form a mixed voltage plane package design; and   a package fabrication system that fabricates the laminate chip package based on the mixed voltage plane package design.   
     
     
         14 . The system of  claim 13 , wherein the first area is under a first chip and wherein the first voltage plane is a source voltage plane. 
     
     
         15 . The system of  claim 14 , wherein the second area is not under a chip and wherein the second preferred voltage plane is the ground plane. 
     
     
         16 . The system of  claim 15 , wherein the design analysis engine identifies a third preferred voltage plane for the first conductive layer within a third area of the laminate package design under a second chip, wherein the third preferred voltage plane is the source voltage plane; and
 wherein the reference plane adjustment engine positions the signal planes, the source voltage planes, and the ground planes within the plurality of conductive layers such that a path of the signal plane maintains a relatively consistent impedance from beneath the second area to beneath the third area by a balanced proximity to a conductive layer connected to the source voltage and a conductive layer connected to the ground potential, without adding layers to the laminate package design.   
     
     
         17 . The system of  claim 13 , wherein the reference plane adjustment engine connects a source voltage plane from the first layer in the first area to a second layer within the two intermediate conductive layers in the second area using one or more vias. 
     
     
         18 . The system of  claim 17 , wherein the reference plane adjustment engine connects the signal plane from the second layer in the first area to a third layer within the two intermediate conductive layers in the second area using one or more vias. 
     
     
         19 . The system of  claim 18 , wherein the reference plane adjustment engine connects a ground plane from the third layer in the first area to the fourth layer in the second area using one or more vias such that the signal plane maintains a balanced proximity to the source voltage plane and the ground plane.