In-pixel kTC noise suppression using circuit techniques

Abstract

A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within each pixel such that the reset voltage and the integration voltage are sampled and stored within the pixel until the voltages are forwarded to a differential amplifier for subtraction.

1 - 52 . (canceled)  
   
   
       53 . An imager pixel comprising: 
 a photosensitive element;    a storage area for storing a reset charge and an image charge from the photosensitive element;    a reset element for resetting the storage area;    a first source follower transistor having a gate connected to the storage area, said first source follower transistor for providing a reset signal based on the reset charge and an image signal based on the image charge;    a capacitor for receiving and storing the reset and image signals provided by the first source follower transistor; and    a second source follower transistor having a gate connected to the capacitor and providing the reset and image signals as pixel output signals to a same column line.    
   
   
       54 . The imager pixel of  claim 53 , wherein each of said pixels further comprise: 
 a column bus switchably coupled to said storage area for receiving said reset voltage level.    
   
   
       55 . The imager pixel of  claim 54 , wherein each of said pixels further comprise: 
 a first source/drain terminal of a load transistor coupled to ground; and    a second source/drain terminal of said load transistor coupled to said first source follower transistor and said capacitor.    
   
   
       56 . The imager pixel of  claim 53 , wherein each of said pixels further comprises: 
 a cascaded integration portion within said reset portion for increasing dynamic range of said pixel.    
   
   
       57 . A semiconductor chip, comprising: 
 an active pixel sensor, said active pixel sensor comprising: 
 a plurality of pixels, wherein each of said pixels comprises: 
 a reset portion for resetting a photosensitive element of said pixel;  
 a capacitor coupled to a source follower transistor having a gate for receiving a charge signal from said photosensitive element;  
 said capacitor coupled to said source follower transistor for storing an output voltage produced by said source follower transistor; and  
 a single output line for transmitting a reset signal and an image signal produced by said source follower transistor.  
 
   
   
   
       58 . The semiconductor chip of  claim 57 , wherein each of said pixels further comprises: 
 a first source/drain terminal of a load transistor coupled to ground; and    a second source/drain terminal of said load transistor coupled to said first source follower transistor and said capacitor.    
   
   
       59 . The semiconductor chip of  claim 57 , wherein each of said pixels further comprises: 
 a cascaded integration portion within said reset portion for increasing dynamic range of said pixel.    
   
   
       60 . A processor system, comprising: 
 a processor; and    an imager device coupled to said processor for sending signals to said processor, said imager device comprising: 
 a plurality of pixels, wherein each of said pixels comprises: 
 a reset portion for resetting a photosensitive element of said pixel;  
 a capacitor coupled to a source follower transistor having a gate for receiving a charge signal from said photosensitive element;  
 said capacitor coupled to said source follower transistor for storing an output voltage produced by said source follower transistor; and  
 a single output line for transmitting an image signal voltage and a reset voltage produced by said output voltage of said source follower transistor.  
 
   
   
   
       61 . The processor system of  claim 60 , wherein each of said pixels further comprises: 
 a first source/drain terminal of a load transistor coupled to ground; and    a second source/drain terminal of said load transistor coupled to said first source follower transistor and said storage capacitor.    
   
   
       62 . The processor system of  claim 60 , wherein each of said pixels further comprises: 
 a cascaded integration portion within said reset portion for increasing dynamic range of said pixel.