Switching Low Noise Amplifier

Abstract

Disclosed are embodiments of an integrated circuit device design adapted to selectively amplify one of multiple received input signals. The device design resides on a machine readable medium, which is used by a design house, customer, or manufacturer to aid in the design and manufacture of at least one embodiment of the integrated circuit device. The device design incorporates at least two first stage transistors and a single second stage transistor. The first stage transistors are adapted to receive input signals from the same or different input signal sources and are each electrically coupled to the second stage transistor. A control circuit design is adapted to individually turn on a selected first stage transistor in conjunction with the second stage transistor, thereby activating a corresponding one of the cascode amplifiers and allowing the input signal received by the selected first stage transistor to be separately amplified.

1 . A design structure instantiated in a machine readable medium for designing and manufacturing an integrated circuit device;
 the integrated circuit device comprising:   a plurality of first transistors, wherein each of said first transistors comprises a first control node;   a second transistor comprising a second control node,   wherein each of said first transistors is adapted to receive and amplify an input signal and to transmit said input signal to said second transistor,   wherein said second transistor is adapted to further amplify said input signal; and   a control circuit electrically coupled to said second transistor and to each of said first transistors, wherein said control circuit is adapted to selectively and individually turn on said first control node of only one of said first transistors simultaneously with said second control node such that only one input signal is amplified at a time.   
   
   
       2 . The integrated circuit device of  claim 1 , further comprising a plurality of first impedance matching circuits, wherein each one of said first impedance matching circuits is electrically coupled between an input signal source and one of said first transistors. 
   
   
       3 . The integrated circuit device of  claim 1 , further comprising a second impedance matching circuit electrically coupled to said second transistor. 
   
   
       4 . The integrated circuit device of  claim 1 , wherein said control circuit is further adapted to turn on said second control node in conjunction with said first control node of each of said first transistors, individually, in response to different predetermined voltages. 
   
   
       5 . The integrated circuit device of  claim 1 , wherein when selectively and individually turned on, said first transistors in series with said second transistor form cascode amplifiers and wherein said cascode amplifiers are tuned to specified frequencies for noise figure and gain. 
   
   
       6 . The integrated circuit device of  claim 5 ,
 wherein said input signal received by each of said first transistors is transmitted from a single input signal source, and   wherein said specified frequencies are different.   
   
   
       7 . The integrated circuit device of  claim 5 ,
 wherein said input signal received by each of said first transistors is transmitted from different input signal sources, and   wherein said specified frequencies are the same.   
   
   
       8 . The integrated circuit device of  claim 5 ,
 wherein said input signal received by each of said first transistors is transmitted from different input signal sources, and   wherein said specified frequencies are different.   
   
   
       9 . The integrated circuit device of  claim 1 , wherein said first transistors and said second transistor each comprise a transistor of a type suitable to be used for gain. 
   
   
       10 . A design structure instantiated in a machine readable medium for designing and manufacturing an integrated circuit device, the integrated circuit device comprising:
 a plurality of first bipolar transistors, wherein each of said first bipolar transistors comprises a first base;   a second bipolar transistor comprising a second base,   wherein each one of said first bipolar transistors is adapted to receive and amplify an input signal and to transmit said input signal to said second bipolar transistor,   wherein said second bipolar transistor is adapted to further amplify said input signal; and   a control circuit electrically coupled to said second bipolar transistor and each of said first bipolar transistors, wherein said control circuit is adapted to selectively and individually turn on said first base of only one of said first bipolar transistors simultaneously with said second base such that only one input signal is amplified at a time.   
   
   
       11 . The integrated circuit device of  claim 10 , further comprising a plurality of first impedance matching circuits, wherein each one of said first impedance matching circuits is electrically coupled between an input signal source and one of said first bipolar transistors. 
   
   
       12 . The integrated circuit device of  claim 10 , further comprising a second impedance matching circuit electrically coupled to said second bipolar transistor. 
   
   
       13 . The integrated circuit device of  claim 10 , wherein said control circuit is further adapted to turn on said second control node in conjunction with said first control node of each of said first transistors, individually, in response to different predetermined voltages. 
   
   
       14 . The integrated circuit device of  claim 10 , wherein when selectively and individually turned on, said first bipolar transistors in series with said second bipolar transistor form cascode amplifiers and wherein said cascode amplifiers are tuned to specified frequencies for noise figure and gain. 
   
   
       15 . The integrated circuit device of  claim 14 ,
 wherein said input signal received by each of said first bipolar transistors is transmitted from a single input signal source, and   wherein said specified frequencies are different.   
   
   
       16 . The integrated circuit device of  claim 14 ,
 wherein said input signal received by each of said first bipolar transistors is transmitted from different input signal sources, and   wherein said specified frequencies are the same.   
   
   
       17 . The integrated circuit device of  claim 14 ,
 wherein said input signal received by each of said first bipolar transistors is transmitted from different input signal sources, and   wherein said specified frequencies are different.   
   
   
       18 . A design structure instantiated in a machine readable medium for designing and manufacturing an integrated circuit device, the integrated circuit device comprising:
 a plurality of first field effect transistors, wherein each of said first field effect transistors comprises a first gate;   a second field effect transistor comprising a second gate,   wherein each one of said first field effect transistors is adapted to receive and amplify an input signal and to transmit said input signal to said second field effect transistor,   wherein said second field effect transistor is adapted to further amplify said input signal; and   a control circuit electrically coupled to said second field effect transistor and each of said first field effect transistors, wherein said control circuit is adapted to selectively and individually turn on said first gate of only one of said first field effect transistors simultaneously with said second gate such that only one input signal is amplified at a time   
   
   
       19 . The integrated circuit device of  claim 18 , further comprising a plurality of first impedance matching circuits, wherein each one of said first impedance matching circuits is electrically coupled between an input signal source and one of said first field effect transistors. 
   
   
       20 . The integrated circuit device of  claim 18 , further comprising a second impedance matching circuit electrically coupled to said second field effect transistor.