Integrated circuit device and electronic instrument

Abstract

An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

1 . An integrated circuit device, comprising: 
 a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and    a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,    wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,    wherein the wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel, and    wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.    
   
   
       2 . The integrated circuit device as defined in  claim 1 , 
 wherein first to Nth latch signals are supplied to the first to Nth divided data line drivers, respectively, and    wherein the first to Nth divided data line drivers latch data supplied from the RAM block based on the first to Nth latch signals.    
   
   
       3 . The integrated circuit device as defined in  claim 2 , 
 wherein, when the identical wordline is selected first time, the first latch signal is set to active so that data supplied from the RAM block in response to the first selection is latched by the first divided data line driver, and    wherein, when the identical wordline is selected Kth time (1≦K≦N; K is an integer), the Kth latch signal is set to active so that data supplied from the RAM block in response to the Kth selection is latched by the Kth divided data line driver.    
   
   
       4 . The integrated circuit device as defined in  claim 2 , 
 wherein the RAM block includes a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,    wherein at least M×N memory cells are arranged in the RAM block along a second direction in which the wordlines extend, and    wherein (M×N)-bit data is supplied to the sense amplifier circuit upon one wordline selection.    
   
   
       5 . The integrated circuit device as defined in  claim 4 , 
 wherein the sense amplifier circuit detects and outputs M-bit data of the (M×N)-bit data based on a sense amplifier select signal.    
   
   
       6 . The integrated circuit device as defined in  claim 5 , 
 wherein the sense amplifier circuit includes a plurality of selective sense amplifiers, and    wherein, each time the identical wordline is selected N times in the one horizontal scan period, each of the selective sense amplifiers receives N-bit data from first to Nth memory cells of M×N memory cells connected with the selected wordline, and detects and outputs 1-bit data from a Kth (1≦K≦N; K is an integer) memory cell of the first to Nth memory cells based on the sense amplifier select signal.    
   
   
       7 . The integrated circuit device as defined in  claim 6 , 
 wherein the sense amplifier select signal is set so that the selective sense amplifier detects and outputs data received from the first memory cell when the identical wordline is selected first time, and detects and outputs data received from the Kth memory cell when the identical wordline is selected Kth time.    
   
   
       8 . The integrated circuit device as defined in  claim 4 , 
 wherein each of the first to Nth divided data line drivers drives one of the data line groups based on the M-bit data supplied from the RAM block, and    wherein, when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line drivers drives M/G data lines.    
   
   
       9 . The integrated circuit device as defined in  claim 4 , 
 wherein each of the first to Nth divided data line drivers drives one of the data line groups based on the M-bit data supplied from the RAM block, and    wherein, when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line drivers includes M/G data line driver cells, and    wherein each of the M/G data line driver cells drives one of the data lines.    
   
   
       10 . The integrated circuit device as defined in  claim 9 , 
 wherein the value “M/G” is a multiple of three when the display panel performs a color display,    wherein the M/G data line driver cells include M/3G R data line driver cells, M/3G G data line driver cells and M/3G B data line driver cells, each of M/3G R data line driver cells driving a data line corresponding to an R pixel, each of M/3G G data line driver cells driving a data line corresponding to a G pixel, and each of M/3G B data line driver cells driving a data line corresponding to a B pixel, and    wherein the M/G data line driver cells are arranged so that the R data line driver cells, the G data line driver cells, and the B data line driver cells are alternately disposed.    
   
   
       11 . The integrated circuit device as defined in  claim 9 , 
 wherein the value “N” is a multiple of three when the display panel performs a color display,    wherein the M/G data line driver cells in a first group when dividing the first to Nth divided data line drivers into three groups include M/G R data line driver cells, each of which drives a data line corresponding to an R pixel,    wherein the M/G data line driver cells in a second group include M/G G data line driver cells, each of which drives a data line corresponding to a G pixel,    wherein the M/G data line driver cells in a third group include M/G B data line driver cells, each of which drives a data line corresponding to a B pixel, and    wherein the M/G data line driver cells are arranged along the second direction.    
   
   
       12 . The integrated circuit device as defined in  claim 4 , 
 wherein each of the first to Nth divided data line drivers includes first to Sth (S is an integer larger than one) subdivided data line drivers into which the divided data line driver is subdivided,    wherein, when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Sth subdivided data line drivers includes M/(G×S) data line driver cells, each of which drives one of the data lines, and    wherein the first to Sth subdivided data line drivers are disposed along the first direction.    
   
   
       13 . The integrated circuit device as defined in  claim 12 , 
 wherein an identical latch signal of the first to Nth latch signals is supplied to each of the first to Sth subdivided data line drivers.    
   
   
       14 . An integrated circuit device, comprising: 
 a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and    a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,    wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,    wherein the wordline control circuit controls (L×J=N) times of reading of data from the RAM block in one horizontal scan period of the display panel, by selecting an identical wordline L times (L is an integer larger than one) and J wordlines (J is an integer larger than one) as the identical wordline selected L times in the one horizontal scan period, and    wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.    
   
   
       15 . An integrated circuit device, comprising: 
 a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and    a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,    wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,    wherein the wordline control circuit sequentially selects N (N is an integer larger than one) different wordlines in one horizontal scan period of the display panel, and selects an identical wordline at least L times (L is an integer larger than one) in one vertical scan period of the display panel; and    wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.    
   
   
       16 . The integrated circuit device as defined in  claim 15 , 
 wherein first to Nth latch signals are supplied to the first to Nth divided data line drivers, respectively, and    wherein the first to Nth divided data line drivers latch data supplied from the RAM block based on the first to Nth latch signals.    
   
   
       17 . The integrated circuit device as defined in  claim 16 , 
 wherein, when the wordlines are selected first time in the one horizontal scan period, the first latch signal is set to active so that data supplied from the RAM block in response to the first selection is latched by the first divided data line driver, and, when the wordlines are selected Kth time (1≦K≦N; K is an integer), the Kth latch signal is set to active so that data supplied from the RAM block in response to the Kth selection is latched by the Kth divided data line driver.    
   
   
       18 . The integrated circuit device as defined in  claim 16 , 
 wherein the RAM block includes a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,    wherein at least M×L memory cells are arranged in the RAM block along a second direction in which the wordlines extend, and    wherein (M×L)-bit data is supplied to the sense amplifier circuit upon one wordline selection.    
   
   
       19 . The integrated circuit device as defined in  claim 18 , 
 wherein each of the first to Nth divided data line drivers drives one of the data line groups based on the M-bit data supplied from the RAM block, and    wherein, when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line drivers includes M/G data line driver cells, and    wherein each of the M/G data line driver cells drives one of the data lines.    
   
   
       20 . The integrated circuit device as defined in  claim 19 , 
 wherein the value “M/G” is a multiple of three when the display panel performs a color display,    wherein the M/G data line driver cells include M/3G R data line driver cells, M/3G G data line driver cells and M/3G B data line driver cells, each of M/3G R data line driver cells driving a data line corresponding to an R pixel, each of M/3G G data line driver cells driving a data line corresponding to a G pixel, and each of M/3G B data line driver cells driving a data line corresponding to a B pixel, and    wherein the M/G data line driver cells are arranged so that the R data line driver cells, the G data line driver cells, and the B data line driver cells are alternately disposed.    
   
   
       21 . The integrated circuit device as defined in  claim 19 , 
 wherein the value “N” is a multiple of three when the display panel performs a color display,    wherein the M/G data line driver cells in a first group when dividing the first to Nth divided data line drivers into three groups include M/G R data line driver cells, each of which drives a data line corresponding to an R pixel,    wherein the M/G data line driver cells in a second group include M/G G data line driver cells, each of which drives a data line corresponding to a G pixel,    wherein the M/G data line driver cells in a third group include M/G B data line driver cells, each of which drives a data line corresponding to a B pixel, and    wherein the M/G data line driver cells are arranged along the second direction.    
   
   
       22 . The integrated circuit device as defined in  claim 18 , 
 wherein each of the first to Nth divided data line drivers includes first to Sth (S is an integer larger than one) subdivided data line drivers into which the divided data line driver is subdivided,    wherein, when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Sth subdivided data line drivers includes M/(G×S) data line driver cells, each of which drives one of the data lines, and    wherein the first to Sth subdivided data line drivers are disposed along the first direction.    
   
   
       23 . The integrated circuit device as defined in  claim 22 , 
 wherein an identical latch signal of the first to Nth latch signals is supplied to each of the first to Sth subdivided data line drivers.    
   
   
       24 . The integrated circuit device as defined in  claim 1 , 
 wherein the wordlines are formed parallel to a direction in which the data lines of the display panel extend.    
   
   
       25 . A driving method comprising: 
 providing a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality or memory cells, and a wordline control circuit;    providing a data line driver block that drives a plurality of data line groups of a display panel based on data supplied from the RAM block, the data line driver block including first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line driver blocks driving a different data line group of the data line groups;    disposing the first to Nth divided data line drivers along a first direction in which the plurality of bitlines extend; and    driving an identical wordline N times from among the plurality of wordlines in one horizontal scan period of the display panel.