US2008119029A1PendingUtilityA1

Wafer scale thin film package

Assignee: CALETKA DAVID VINCENTPriority: Jul 27, 2000Filed: Jan 17, 2008Published: May 22, 2008
Est. expiryJul 27, 2020(expired)· nominal 20-yr term from priority
H10W 90/724H10W 72/07254H10W 72/07236H10W 72/07227H10W 72/01204H10W 72/856H10W 72/354H10W 72/352H10W 72/351H10W 72/331H10W 72/325H10W 72/281H10W 72/242H10W 72/241H10W 72/073H10W 72/072H10W 72/29H10W 70/60H10W 70/05H10W 90/00H10W 74/129H10W 74/15H10W 74/012H10W 72/30H10W 20/49H05K 3/3436Y02P70/50Y10S438/94H05K 2201/2036H05K 2201/10977Y10S438/977
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Claims

Abstract

A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

Claims

exact text as granted — not AI-modified
1 - 29 . (canceled) 
     
     
         30 . A wafer scale method of forming a chip modules, having flexible thin film redistribution layer thereon comprising:
 depositing a thin layer of insulating material directly on said wafer;   forming vias in said layer of insulating material to the chip electrical contacts on said wafer;   filing said vias with a conductive material;   forming a metallurgical pattern on said thin layer of insulating material and in contact with said conductive material of said vias;   alternating said steps of forming layers of insulating material with metal filled vias and forming said metallurgical patterns on said layer of insulating material to thereby form a selected redistribution pattern for chip signal and power redistribution;   forming a pattern of metal filled vias in the final layer of insulating material matching the pattern of contact pads on the substrate to which said chip modules will be attached;   forming pads on said metal filled vias of said final layer of insulating material; and   dicing said wafer to form said chip modules.   
     
     
         31 . The method as set forth in  claim 30  wherein said flexible insulating material is a polymer. 
     
     
         32 . The method as set forth in  claim 30  wherein said pads are BGA pads. 
     
     
         33 - 42 . (canceled) 
     
     
         43 . A wafer scale method of forming a chip module, comprising:
 forming a flexible thin film directly on a wafer by depositing a flexible insulating material directly on the surface of said wafer having connection pads thereon; and   forming metal filled vias in said layer flexible insulating material to connect to said connection pads on said wafer;   forming metallurgy on said flexible insulating material to connect to said metal filled vias;   repeating the above steps of forming a flexible thin film of insulating material, metal filled vias and metallurgy to form a multilayer redistribution thin film;   forming vias in the final thin film layer of insulating material having a pattern matching the pattern of connection pads on the substrate to which it is to be attached; and   forming a pattern of pads on said vias in said final thin film layer of insulating material.   
     
     
         44 . The method as set forth in  claim 43  wherein said flexible insulating material is polymer. 
     
     
         45 . the method as set forth in  claim 43  comprising the further step of dicing said wafer to form chip modules ready for packaging.

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