Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires

Abstract

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

1 . A process for making a transistor device, comprising:
 a. providing a device substrate;   b. depositing a first conductive polymer layer on the device substrate;   c. defining one or more gate contact regions in the conductive polymer layer;   d. depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level;   e. depositing a second conductive polymer layer on the plurality of nanowires; and   f. forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.   
     
     
         2 . The process of  claim 1 , further comprising aligning the nanowires substantially parallel to their long axis. 
     
     
         3 . The process of  claim 1 , wherein defining one or more gate contact regions comprises masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive. 
     
     
         4 . The process of  claim 1 , further comprising forming a gate dielectric layer on the first conductive polymer layer. 
     
     
         5 . The process of  claim 4 , wherein the plurality of nanowires is deposited on the gate dielectric layer. 
     
     
         6 . The process of  claim 1 , wherein defining the source and drain regions in the second conductive polymer layer comprises masking at least two or more portions of the second conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive. 
     
     
         7 . The process of  claim 1 , wherein depositing the first and/or second conductive polymer layers comprises using a process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting. 
     
     
         8 . The process of  claim 1 , further comprising depositing a metal or doped silicon in the source and drain contact regions. 
     
     
         9 . The process of  claim 1 , further comprising forming a gate electrode in the gate contact region. 
     
     
         10 . A process for making a transistor device, comprising:
 a. providing a substrate;   b. depositing a conductive polymer layer incorporating a plurality of nanowires on the substrate;   c. defining source and drain contact regions in the conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain contact regions; and   d. forming a gate on the conductive polymer layer.   
     
     
         11 . The process of  claim 10 , further comprising aligning the nanowires substantially parallel to their long axis. 
     
     
         12 . The process of  claim 10 , wherein defining the source and drain contact regions comprises masking two or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive. 
     
     
         13 . The process of  claim 10 , wherein depositing the conductive polymer layer comprises using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting. 
     
     
         14 . The process of  claim 10 , further comprising depositing a metal or doped silicon in the source and drain contact regions. 
     
     
         15 . The process of  claim 10 , wherein forming said gate comprises depositing a metal on a portion of said conductive polymer layer. 
     
     
         16 . The process of  claim 10 , wherein the nanowires comprise a layer of oxide deposited on at least a portion of the nanowires. 
     
     
         17 . The process of  claim 16 , further comprising removing a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions. 
     
     
         18 . The process of  claim 10 , wherein said nanowires are formed as a monolayer film, a sub monolayer film, or a multi-layer film. 
     
     
         19 . The process of  claim 10 , wherein the substrate is made from a plastic material. 
     
     
         20 . A process for making a transistor device, comprising:
 a. providing a substrate;   b. depositing a first conductive polymer layer on the substrate;   c. defining one or more gate contact regions in the first conductive polymer layer;   d. depositing a second conductive polymer layer having a plurality of nanowires incorporated therein over the first conductive polymer layer; and   e. forming source and drain contact regions in the second conductive polymer layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.   
     
     
         21 . The process of  claim 20 , further comprising aligning the nanowires substantially parallel to their long axis. 
     
     
         22 . The process of  claim 20 , wherein defining the gate contact region comprises masking one or more portions of the first conductive polymer layer, and exposing the unmasked portions to ultraviolet energy to render the unmasked portions highly resistive. 
     
     
         23 . The process of  claim 20 , wherein depositing the first and/or second conductive polymer layers comprises using a coating process selected from spin coating, casting, printing, wire roding, spraying, or brush-painting. 
     
     
         24 . The process of  claim 20 , further comprising depositing a metal or doped silicon in the gate, source and/or drain contact regions. 
     
     
         25 . The process of  claim 20 , further comprising forming a gate electrode in the gate contact region. 
     
     
         26 . The process of  claim 20 , wherein the nanowires comprise a layer of oxide deposited on at least a portion of the nanowires. 
     
     
         27 . The process of  claim 26 , further comprising removing a portion of the oxide layer at the ends of the nanowires proximal the source and drain contact regions of the device to improve ohmic contact between the nanowires and the source and drain contact regions. 
     
     
         28 . The process of  claim 20 , wherein said nanowires are formed as a monolayer film, a sub monolayer film, or a multi-layer film. 
     
     
         29 . The process of  claim 20 , wherein the substrate is made from a plastic material.