Semiconductor devices with buried isolation regions

Abstract

Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

1 . A semiconductor structure, comprising:
 a silicon substrate;   a gate dielectric on a top surface of said silicon substrate;   a gate electrode on a top surface of said gate dielectric;   a source and a drain in said substrate and on opposite sides of said gate electrode; and   a first void in said substrate under said source and a second void in said substrate under said drain.   
   
   
       2 . The structure of  claim 1 , wherein a top most surface of said first or said second void is between about 20 nanometers and about 300 nanometers below a top surface of said substrate. 
   
   
       3 . The structure of  claim 1 , wherein said first and said second voids do not extend under said gate electrode. 
   
   
       4 . The structure of  claim 1 , wherein said first and said second voids extend partially under said gate electrode. 
   
   
       5 . The structure of  claim 1 , wherein said first and second voids are entirely with a well region containing said source and said drain. 
   
   
       6 . A semiconductor structure, comprising:
 a silicon substrate;   a gate dielectric on a top surface of said silicon substrate;   a gate electrode on a top surface of said gate dielectric;   a source and a drain in said substrate and on opposite sides of said gate electrode; and   a first group of voids in said substrate under said source and a second group of voids in said substrate under said drain.   
   
   
       7 . The structure of  claim 6 , wherein a top most surface of a void closest to said top surface of said substrate of said first and said second group of voids is between about 20 nanometers and about 300 nanometers below said top surface of said substrate. 
   
   
       8 . The structure of  claim 6 , wherein said first and said second group of voids do not extend under said gate electrode. 
   
   
       9 . The structure of  claim 6 , wherein said first and said second group of voids extend partially under said gate electrode. 
   
   
       10 . The structure of  claim 6 , wherein said at least one spatial extent of at least one void of said first group of voids and at least one spatial extent of at least one void of said second group of voids is between about 2 nanometers and about 100 nanometers.