Methods and apparatus for testing a link between chips

Abstract

In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.

1 . A method of testing a link between a first chip and a second chip, comprising:
 while operating in a test mode:
 transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and 
 performing cyclic redundancy checking (CRC) on the test data to test the link. 
   
   
   
       2 . The method of  claim 1  wherein one or more packets of a first size are employed to transmit data via the link while operating in a functional mode; and
 further comprising employing one or more packets of a second size, larger than the first size, to transmit the test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link while operating in the test mode;   wherein the second packet size enables a predetermined minimum number of contiguous test data bits required to test the link to be transmitted via the link.   
   
   
       3 . The method of  claim 2  wherein performing CRC on the test data to test the link includes:
 before transmitting the test data from the first chip:
 calculating a first CRC value based on portions of test data included in a packet of the second size to be transmitted; and 
 inserting the first CRC value in the packet of the second size to be transmitted; and 
   while receiving the packet of the second size in the second chip:
 calculating a second CRC value based on portions of the test data included in the received packet of the second size; and 
 comparing the second CRC value with the first CRC value. 
   
   
   
       4 . The method of  claim 2  wherein transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link includes transmitting at least the predetermined minimum number of contiguous test data bits required to test the link. 
   
   
       5 . The method of  claim 4  wherein transmitting at least the predetermined minimum number of contiguous test data bits required to test the link includes transmitting at least the predetermined minimum number of contiguous test data bits required to at least one of stress test and debug the link. 
   
   
       6 . The method of  claim 1  further comprising reducing an area required to test the link on at least one of the first and second chips. 
   
   
       7 . A system for testing a link, comprising:
 a first chip including a first portion of cyclic redundancy checking (CRC) logic;   a second chip including a second portion of the CRC logic; and   a link coupled to the first and second chips;   wherein the system is adapted to:
 while operating in a test mode:
 transmit test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and 
 test the link by performing CRC on the test data using the CRC logic. 
 
   
   
   
       8 . The system of  claim 7  wherein the system is further adapted to:
 employ one or more packets of a first size to transmit data via the link while operating in a functional mode; and   employ one or more packets of a second size, larger than the first size, to transmit the test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link while operating in the test mode;   wherein the second packet size enables a predetermined minimum number of contiguous test data bits required to test the link to be transmitted via the link.   
   
   
       9 . The system of  claim 8  wherein the system is further adapted to:
 before transmitting the test data from the first chip:
 calculate a first CRC value based on portions of test data included in a packet of the second size to be transmitted; and 
 insert the first CRC value in the packet of the second size to be transmitted; and 
   while receiving the packet of the second size in the second chip:
 calculate a second CRC value based on portions of the test data included in the received packet of the second size; and 
 compare the second CRC value with the first CRC value. 
   
   
   
       10 . The system of  claim 8  wherein the system is further adapted to transmit at least the predetermined minimum number of contiguous test data bits required to test the link. 
   
   
       11 . The system of  claim 10  wherein the system is further adapted to transmit at least the predetermined minimum number of contiguous test data bits required to at least one of stress test and debug the link. 
   
   
       12 . The system of  claim 7  wherein the system is further adapted to reduce an area required to test the link on at least one of the first and second chips. 
   
   
       13 . A data packet structure to be employed in the test mode of the method of  claim 1 , comprising:
 a first portion adapted to store a CRC value and a value indicating a start of the data packet; and   a second portion adapted to contiguously store user-defined data such that a predetermined minimum number of contiguous user-defined data bits required to test the link may be transmitted via the link.   
   
   
       14 . The data packet structure of  claim 13  wherein the user-defined data is test data. 
   
   
       15 . The system of  claim 9 , wherein the second CRC logic of the first receive side logic and the fourth CRC logic of the second receive side logic include control logic adapted to enable the CRC logic to calculate the second CRC value based on data received in packets of the second size. 
   
   
       16 . The system of  claim 15 , wherein the control logic is adapted to reduce a frequency at which a CRC value is reset during operation in the test mode.