End-to-end data integrity protection for pci-express based input/output adapter

Abstract

Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.

1 . A method, in a data processing system, for protecting the integrity of data transferred between an input/output bus and a network, the method comprising:
 generating a first Cyclic Redundancy Check value on an interface between the input/output bus and an adapter for first data transferred from the input/output bus to the network;   checking a second Cyclic Redundancy Check value on the interface between the input/output bus and the adapter for second data transferred from the network to the input/output bus;   checking the first Cyclic Redundancy Check value for the first data prior to an interface between the adapter and the network; and   generating a third Cyclic Redundancy Check value for the first data prior to the interface between the adapter and the network after checking the first Cyclic Redundancy Check value.   
   
   
       2 . (canceled) 
   
   
       3 . (canceled) 
   
   
       4 . The method according to  claim 1 , and further comprising:
 checking a fourth Cyclic Redundancy Check value for the first data on the interface between the input/output bus and the adapter prior to generating the first Cyclic Redundancy Check value.   
   
   
       5 . The method according to  claim 1 , and further comprising:
 generating a fifth Cyclic Redundancy Check value for the second data on the interface between the input/output bus and the adapter after checking the second Cyclic Redundancy Check value.   
   
   
       6 . The method according to  claim 1 , wherein the first data comprises a first data packet and the second data comprises a second data packet. 
   
   
       7 . The method according to  claim 6 , and further comprising:
 storing the first Cyclic Redundancy Check value in a transmit packet buffer on the adapter and storing the second Cyclic Redundancy Check value in a receive packet buffer on the adapter.   
   
   
       8 . The method according to  claim 1 , wherein the input/output bus comprises a Peripheral Component Interconnect input/output bus architecture. 
   
   
       9 - 19 . (canceled) 
   
   
       20 . A computer program product that is stored in a computer readable medium for protecting the integrity of data transferred between an input/output bus and a network, comprising:
 first instructions for generating a first Cyclic Redundancy Check value on an interface between the input/output bus and an adapter for first data transferred from the input/output bus to the network;   second instructions for checking a second Cyclic Redundancy Check value on the interface between the input/output bus and the adapter for second data transferred from the network to the input/output bus;   third instructions for checking the first Cyclic Redundancy Check value for the first data prior to an interface between the adapter and the network; and   fourth instructions for generating a third Cyclic Redundancy Check value for the first data prior to the interface between the adapter and the network after checking the first Cyclic Redundancy Check value.   
   
   
       21 . (canceled) 
   
   
       22 . (canceled) 
   
   
       23 . The computer program product according to  claim 20 , and further comprising:
 fifth instructions for checking a fourth Cyclic Redundancy Check value for the first data on the interface between the input/output bus and the adapter prior to generating the first Cyclic Redundancy Check value.   
   
   
       24 . The computer program product according to  claim 20 , and further comprising:
 sixth instructions for generating a fifth Cyclic Redundancy Check value for the second data on the interface between the input/output bus and the adapter after checking the second Cyclic Redundancy Check value.   
   
   
       25 . The computer program product according to  claim 20 , wherein the first data comprises a first data packet and the second data comprises a second data packet, and further comprising:
 seventh instructions for storing the first Cyclic Redundancy Check value in a transmit packet buffer on the adapter and storing the second Cyclic Redundancy Check value in a receive packet buffer on the adapter.   
   
   
       26 . The computer program product according to  claim 20 , wherein the input/output bus comprises a Peripheral Component Interconnect input/output bus architecture.