Data processing in digital systems

Abstract

A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

1 . A structure, comprising:
 an FPGA (Field-Programmable Gate Array) including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB (Configurable Logic Block),
 wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address, 
 wherein a first subset of the FPGA elements is configured to form a first functional block, 
 wherein the first functional block comprises a mapped location register residing in one or more FPGA CLBs of the first functional block, and 
 wherein the mapped location register stores the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block. 
   
   
   
       2 . The structure of  claim 1 ,
 wherein the first functional block further comprises a mapped destination register residing in one or more FPGA CLBs of the first functional block, and   wherein the mapped destination register stores the address of a destination FPGA element, the address of the destination FPGA element being specified as the destination of the first functional block.   
   
   
       3 . The structure of  claim 1 , further comprising a first localized IO (Input/Output) circuit and a second localized IO circuit both electrically coupled to the FPGA,
 wherein the first functional block is formed via the first localized IO circuit, and   wherein the first functional block is configured to move to the second localized IO circuit.   
   
   
       4 . The structure of  claim 3 , wherein the first functional block is configured to move to the second localized IO circuit within a time limit in terms of clock cycles. 
   
   
       5 . The structure of  claim 1 , wherein the FPGA further comprises connections electrically coupling each FPGA element to surrounding FPGA elements such that the contents of all FPGA elements in a functional block can be transferred to their non-adjacent FPGA elements in one clock cycle. 
   
   
       6 . A method for operating an FPGA, the method comprising the steps of:
 providing an FPGA including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address;   forming a first functional block on a first subset of the FPGA elements;   providing in the first functional block a mapped location register residing in one or more FPGA CLBs of the first functional block; and   using the mapped location register to receive and store the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block.   
   
   
       7 . The method of  claim 6 , further comprising the steps of:
 providing further in the first functional block a mapped destination register residing in one or more FPGA CLBs of the first functional block; and   using the mapped destination register to receive and store the address of a destination FPGA element, the address of the destination FPGA element being specified as the destination of the first functional block.   
   
   
       8 . The method of  claim 6 , wherein the step of forming the first functional block on the first subset of the FPGA elements comprises the steps of:
 providing a first localized IO (Input/Output) circuit and a second localized IO circuit, both electrically coupled to the FPGA; and   forming the first functional block via the first localized IO circuit.   
   
   
       9 . The method of  claim 8 , further comprising the step of moving the first functional block to the second localized IO circuit within a time limit in terms of clock cycles. 
   
   
       10 . The method of  claim 6 , further comprising the step of providing connections electrically coupling each FPGA element to surrounding FPGA elements such that the contents of all FPGA elements in a functional block can be transferred to their non-adjacent FPGA elements in one clock cycle.