Extracting a Maximum Pulse Width of a Pulse Width Limiter

Abstract

An apparatus for extracting a maximum pulse width of a pulse width limiter is provided. The apparatus performs such extraction using a circuit that is configured to eliminate a majority of delay cells. The elimination of delay cells is made possible by replacing an OR gate in the circuit configuration with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

1 - 11 . (canceled) 
   
   
       12 . An apparatus for determining a maximum pulse width of a pulse width limiter, comprising:
 at least one pulse width limiter;   a delay circuit element coupled to the at least one pulse width limiter; and   an output clock generation circuit element coupled to the delay circuit element, wherein:   the at least one pulse width limiter receives an input signal and limits a pulse width of the received input signal to generate a first intermediate signal;   the delay circuit element delays the first intermediate signal by a known amount to generate a set signal, and   the output clock generation circuit element asserts a clock output signal in response to assertion of the set signal and de-asserts the clock output signal in response to a receipt of a reset signal, and wherein the asserted clock output signal is representative of the maximum pulse width of the pulse width limiter,   wherein the at least one pulse width limiter comprises a plurality of pulse width limiters arranged in series to thereby provide a series of pulse width limiters, and wherein a first pulse width limiter limits the pulse width of the received known clock signal to generate the first intermediate signal, and wherein a last pulse width limiter in the plurality of pulse width limiters outputs the reset signal.   
   
   
       13 . The apparatus of  claim 12 , wherein the delay circuit element is associated with the first pulse width limiter. 
   
   
       14 . The apparatus of  claim 13 , wherein only the first pulse width limiter in the plurality of pulse width limiters has an associated delay circuit. 
   
   
       15 . The apparatus of  claim 12 , wherein the known amount by which the intermediate signal is delayed is (N−1)τ, where N is a number of pulse width limiters in the plurality of pulse width limiters, and T is a fixed amount of time by which a rising edge of the input signal is delayed by the first pulse width limiter. 
   
   
       16 . An apparatus for determining a maximum pulse width of a pulse width limiter, comprising:
 at least one pulse width limiter;   a delay circuit element coupled to the at least one pulse width limiter; and   an output clock generation circuit element coupled to the delay circuit element, wherein:   the at least one pulse width limiter receives an input signal and limits a pulse width of the received input signal to generate a first intermediate signal;   the delay circuit element delays the first intermediate signal by a known amount to generate a set signal, and   the output clock generation circuit element asserts a clock output signal in response to assertion of the set signal and de-asserts the clock output signal in response to a receipt of a reset signal, and wherein the asserted clock output signal is representative of the maximum pulse width of the pulse width limiter,   wherein the output clock generation circuit element is a re-settable latch.   
   
   
       17 . The apparatus of  claim 16 , wherein the re-settable latch is an edge triggered re-settable latch. 
   
   
       18 . The apparatus of  claim 12 , wherein each pulse width limiter in the plurality of pulse width limiters, with the exception of the last pulse width limiter, has an associated inverter that inverts an output of the associated pulse width limiter and provides the inverted output as an input to a next pulse width limiter in the series of pulse width limiters. 
   
   
       19 . The apparatus of  claim 12 , wherein the assertion of the clock output signal has a pulse width of NT max , where N is a number of pulse width limiters in the plurality of pulse width limiters and T max  is a maximum pulse width of the pulse width limiters. 
   
   
       20 . The apparatus of  claim 19 , wherein a maximum pulse width for a pulse width limiter is determined by dividing the pulse width of the asserted clock output signal by the number of pulse width limiters in the plurality of pulse width limiters. 
   
   
       21 . The apparatus of  claim 12 , wherein the output clock generation circuit element is a re-settable latch.