Data striping to flash memory

Abstract

In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller.

1 . An apparatus, comprising:
 an SATA to ATA bridge;   an ATA to USB bridge coupled to the SATA to ATA bridge;   a USB interface coupled to the ATA to USB bridge;   a first FLASH memory controller coupled to the USB interface;   a first FLASH memory module coupled to the first FLASH memory controller;   a second FLASH memory controller coupled to the USB interface;   and   a second FLASH memory module coupled to the second FLASH memory controller.   
   
   
       2 . The apparatus of  claim 1 , further comprising:
 a buffer coupled to the ATA to USB bridge.   
   
   
       3 . The apparatus of  claim 2 , further comprising:
 a third FLASH memory controller coupled to the USB interface;   and   a third FLASH memory module coupled to the third FLASH memory controller.   
   
   
       4 . The apparatus of  claim 3 , further comprising:
 a fourth FLASH memory controller coupled to the USB interface;   and   a fourth FLASH memory module coupled to the fourth FLASH memory controller.   
   
   
       5 . The apparatus of  claim 4 , further comprising:
 a fifth FLASH memory module coupled to the first FLASH memory controller;   a sixth FLASH memory module coupled to the second FLASH memory controller;   a seventh FLASH memory module coupled to the third FLASH memory controller;   and   an eighth FLASH memory module coupled to the fourth FLASH memory controller.   
   
   
       6 . The apparatus of  claim 5 , wherein:
 the ATA to USB interface and the buffer are implemented as an FPGA.   
   
   
       7 . The apparatus of  claim 6 , further comprising:
 a drive identifier EEPROM coupled to the FPGA.   
   
   
       8 . The apparatus of  claim 6 , further comprising:
 a connector coupled to the FPGA.   
   
   
       9 . The apparatus of  claim 8 , further comprising:
 a separate daughter board, the daughter board including:   a mating connector coupled to the connector;   a fifth FLASH memory controller coupled to the mating connector;   a ninth FLASH memory module coupled to the fifth FLASH memory controller;   a sixth FLASH memory controller coupled to the mating connector;   and   a tenth FLASH memory module coupled to the sixth FLASH memory controller.   
   
   
       10 . The apparatus of  claim 9 , wherein:
 the daughter board further includes:   an eleventh FLASH memory module coupled to the fifth FLASH memory controller;   a twelfth FLASH memory module coupled to the sixth FLASH memory controller;   a seventh FLASH memory controller coupled to the mating connector;   a thirteenth FLASH memory module coupled to the seventh FLASH memory controller;   a fourteenth FLASH memory module coupled to the seventh FLASH memory controller;   an eighth FLASH memory controller coupled to the mating connector;   a fifteenth FLASH memory module coupled to the eighth FLASH memory controller;   and   a sixteenth FLASH memory module coupled to the eighth FLASH memory controller.   
   
   
       11 . The apparatus of  claim 10 , wherein:
 the daughter board further includes:   a USB interface coupled to the mating connector, the USB interface coupled between the mating connector and the fifth FLASH memory controller, the sixth FLASH memory controller, the seventh FLASH memory controller and the eighth FLASH memory controller.   
   
   
       12 . The apparatus of  claim 6 , further comprising:
 means for identifying the apparatus electronically.   
   
   
       13 . A method, comprising:
 receiving data via an SATA bus;   translating the data into ATA format;   separating the data into stripes;   packaging the data for USB transmission;   transferring the data in USB format;   and   storing the data in a set of FLASH memory modules.   
   
   
       14 . The method of  claim 13 , further comprising:
 buffering the data.   
   
   
       15 . The method of  claim 14 , further comprising:
 receiving a data request in SATA format;   translating the request into ATA format;   translating the request into USB format;   relaying the request to the set of FLASH memory modules;   retrieving corresponding data from the set of FLASH memory modules;   transferring the corresponding data in USB format;   transforming the corresponding data to ATA format;   transforming the corresponding data to SATA format;   and   transferring the corresponding data as a response to the request.   
   
   
       16 . The method of  claim 15 , further comprising:
 providing a drive identification responsive to a request.   
   
   
       17 . A method, comprising:
 receiving a data request in SATA format;   translating the request into USB format;   relaying the request to memory;   retrieving corresponding data from memory;   transferring the corresponding data in USB format;   transforming the corresponding data to SATA format;   and   transferring the corresponding data as a response to the request.   
   
   
       18 . The method of  claim 17 , further comprising:
 translating the request into ATA format;   transforming the corresponding data to ATA format;   
   
   
       19 . The method of  claim 18 , further comprising:
 buffering the data request.   
   
   
       20 . The method of  claim 17 , further comprising:
 providing a drive identification responsive to a request.