US2008149907A1PendingUtilityA1

Complementary Resistive Memory Structure

Assignee: HSU SHENG TENGPriority: Sep 30, 2004Filed: Jan 7, 2008Published: Jun 26, 2008
Est. expirySep 30, 2024(expired)· nominal 20-yr term from priority
Inventors:Sheng Teng Hsu
G11C 13/0011
37
PatentIndex Score
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Claims

Abstract

A complementary resistive memory structure is provided comprising a common source electrode and a first electrode separated from the common source electrode by resistive memory material; and a second electrode adjacent to the first electrode and separated from the common source electrode by resistive memory material, along with accompanying circuitry and methods of programming and reading the complementary resistive memory structure.

Claims

exact text as granted — not AI-modified
1 - 8 . (canceled) 
     
     
         9 . A complementary resistive memory structure comprising:
 a common source electrode;   a first electrode separated from the common source electrode by a resistive memory material; and   a second electrode adjacent to the first electrode and separated from the common source electrode by the resistive memory material.   
     
     
         10 . The memory structure of  claim 9 , wherein the first memory resistor comprises a colossal magnetoresistance (CMR) material. 
     
     
         11 . The memory structure of  claim 9 , wherein the first memory resistor comprises Pr 1-x Ca x MnO 3  (PCMO). 
     
     
         12 . The memory structure of  claim 9 , wherein the first memory resistor comprises Gd 1-x Ca x BaCo 2 O 5 + 5 . 
     
     
         13 . The memory structure of  claim 9 , further comprising:
 a first active transistor connected between the first electrode and a first load transistor; which is connected between a drain voltage and the first active transistor at a first active transistor drain; and a first output connected at the first active drain;   a second active transistor connected between the second electrode and a second load transistor; which is connected between a drain voltage and the second active transistor at a second active transistor drain; and a second output connected at the second active drain; and   a word line connected to a first gate of the first active transistor and to a second gate of the second active transistor.   
     
     
         14 - 18 . (canceled)

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