US2008150997A1PendingUtilityA1

Method Of Manufacturing Printhead ICS Incorporating Mems Inkjet Nozzles

Assignee: SILVERBROOK RES PTY LTDPriority: Dec 2, 2002Filed: Mar 6, 2008Published: Jun 26, 2008
Est. expiryDec 2, 2022(expired)· nominal 20-yr term from priority
G06F 21/71B41J 2/04508H03K 5/1252G06F 21/74G06F 21/78B41J 2202/20B41J 2/04541H04N 1/405Y10T29/49401B41J 2/0451B41J 2/04586G06F 21/64B41J 2/04543G06F 21/73B41J 2/04573B41J 2/04528G06F 21/57Y10S707/99939B41J 2/04505G06F 21/554Y10S707/99933G06F 21/575B41J 2/04563
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Claims

Abstract

A method of manufacturing a printhead integrated circuit incorporating microelectromechanical inkjet nozzle systems is provided. The method includes laying out a plurality of first and second reticle exposed areas in sequential arrangement so that a first end of each first reticle exposed area interconnects with either a second end of an adjacent first reticle exposed area or a first end of an adjacent second reticle exposed area and the second end of each first reticle exposed area interconnects with either the first end of an adjacent first reticle exposed area or a second end of an adjacent second reticle exposed area. Each first reticle exposed area has nozzle logic circuitry and each second reticle exposed area has connection pads for connecting the nozzle logic circuitry to power and data.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a printhead integrated circuit incorporating microelectromechanical inkjet nozzle systems, the method comprising the steps of:
 laying out a plurality of first and second reticle exposed areas in sequential arrangement so that a first end of each first reticle exposed area interconnects with either a second end of an adjacent first reticle exposed area or a first end of an adjacent second reticle exposed area and the second end of each first reticle exposed area interconnects with either the first end of an adjacent first reticle exposed area or a second end of an adjacent second reticle exposed area,   wherein each first reticle exposed area has nozzle logic circuitry and each second reticle exposed area has connection pads for connecting the nozzle logic circuitry to power and data.   
     
     
         2 . A method according to  claim 1 , wherein the plurality of first reticle exposed areas are laid out to seal the integrated circuit. 
     
     
         3 . A method according to  claim 1 , wherein the plurality of first reticle exposed areas are laid out to form a feedback circuit. 
     
     
         4 . A method according to  claim 1 , comprising forming a plurality of reticle exposed arrays with each reticle exposed array comprising a plurality of first reticle exposed areas and a plurality of second reticle exposed areas. 
     
     
         5 . A method according to  claim 4 , wherein each reticle exposed array is positionally offset relative to bordering reticle exposed arrays. 
     
     
         6 . A method according to  claim 1 , wherein each first reticle exposed area and each second reticle exposed area has a maximum longitudinal length of 23 millimeters.

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