Memory device, memory controller and memory system

Abstract

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

1 . A memory device, comprising:
 a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and   a control circuit, which, in response to a background refresh command and refresh burst length information, causes the memory cores within refresh target banks to successively execute refresh operation a number of times corresponding to the refresh burst length information.   
     
     
         2 . A memory device which is operated in response to a command from a memory controller, the memory device comprising:
 a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and   a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, while the memory cores within the refresh target banks is executing the refresh operation, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command.   
     
     
         3 . The memory device according to  claim 2 , further comprising a refresh address counter which counts refresh target addresses within each of the plurality of banks or within each of a plurality of groups of the plurality of banks, wherein
 the control circuit has:   a background refresh controller which outputs refresh control signals to the set refresh target banks in response to the background refresh command;   a refresh burst length register in which the refresh burst length is set; and   a core controller which is provided in each of the plurality of banks, and, in response to the background refresh control signals, causes the memory cores to execute refresh operation on the addresses of the refresh address counter a number of times corresponding to the refresh burst length set in the refresh burst length register.   
     
     
         4 . The memory device according to  claim 2 , wherein
 a refresh block count which indicates the number of memory blocks activated simultaneously in a single refresh cycle is supplied, and   the control circuit causes the refresh target banks to execute the refresh operation a number of times corresponding to the set refresh burst length, in response to the background refresh command, the refresh operation being performed for simultaneously activating the memory blocks for the number of the refresh block count.   
     
     
         5 . The memory device according to  claim 3 , wherein the background refresh command and the refresh burst length are inputted simultaneously, the refresh burst length register is provided in each of the banks, and the inputted refresh burst length is set into the refresh burst length register within the refresh target bank. 
     
     
         6 . The memory device according to  claim 4 , further comprising a refresh block count register, wherein
 the background refresh command and the refresh block count are inputted simultaneously, and   the inputted refresh block count is set into the refresh block count register.   
     
     
         7 . The memory device according to  claim 3 , wherein
 the refresh burst length register is provided within a mode register,   a mode register set command and the refresh burst length are inputted simultaneously, and   the inputted refresh burst length is set into the refresh burst length register provided within the mode register.   
     
     
         8 . The memory device according to  claim 4 , wherein
 the refresh block count register is provided within a mode register,   a mode register set command and the refresh block count are inputted simultaneously, and   the inputted refresh block count is set into the refresh block count register provided within the mode register.   
     
     
         9 . The memory device according to  claim 3 , wherein during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times that is obtained by adding the refresh burst length to the remaining number of times of the refresh operation. 
     
     
         10 . The memory device according to  claim 3 , wherein during the refresh operation executed a number of times corresponding to the refresh burst length, the core controller causes, in response to a newly inputted background refresh command, the memory cores within the refresh target banks to successively execute the refresh operation a number of times corresponding to the refresh burst length, regardless of the remaining number of times of the refresh operation. 
     
     
         11 . The memory device according to  claim 3 , wherein the core controller causes, in response to a refresh-all command, the memory cores within the refresh target banks to repeatedly execute the refresh operation from the address of the refresh address counter for the remaining addresses. 
     
     
         12 . The memory device according to  claim 3 , wherein during the refresh operation performed a number of times corresponding to the refresh burst length, the core controller causes the memory cores within the refresh target banks to stop the refresh operation, in response to a background refresh stop command. 
     
     
         13 . The memory device according to  claim 12 , wherein, in response to the background refresh stop command, the core controller does not start a subsequent refresh operation after causing the memory cores within the refresh target banks to end the refresh operation that is being executed. 
     
     
         14 . The memory device according to  claim 3 , wherein, on the basis of setting of an active refresh interlock flag in the mode register, the background refresh controller supplies the background refresh control signals to banks other than an access target bank corresponding to a bank address to be inputted, in response to a normal memory operation command. 
     
     
         15 . The memory device according to  claim 3 , wherein
 the core controller has a refresh-burst length counter for count up in every refresh operation, and   the core controller resets the refresh burst length counter in response to the background refresh command, and causes the memory cores within the refresh target banks to execute the refresh operation until a counter value of the refresh burst length counter reaches the refresh burst length that is set in the refresh burst length register.   
     
     
         16 . The memory device according to  claim 3 , wherein
 the core controller has a refresh burst length counter for counted down in every refresh operation, and   the core controller sets the refresh burst length into the refresh burst length counter in response to the background refresh command, and causes the memory cores within the refresh target banks to execute the refresh operation until a counter value of the refresh burst length counter reaches zero.   
     
     
         17 . A memory device which is operated in response to a command sent from a memory controller, the memory device comprising:
 a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and   a control circuit which controls operation of the memory cell arrays within the banks, wherein   each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and   during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, the control circuit causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command corresponding to the horizontal access, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.   
     
     
         18 . The memory device according to  claim 17 , wherein, during a period of rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the control circuit causes the memory cores within the banks selected by the bank addresses and within banks adjacent to the selected banks, to execute the normal memory operation in response to the normal operation command, and prohibits the refresh operation during the normal memory operation. 
     
     
         19 . A memory system, comprising:
 a memory controller; and   a memory device which is operated in response to a command from the memory controller, wherein   the memory device has:   a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and   a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, during the refresh operation executed by the memory cores within the refresh target banks, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command.   
     
     
         20 . A memory controller which controls a memory device having: a plurality of banks that respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cores within the plurality of banks,
 the memory controller comprising:   a sequencer which, in response to an access request from a host device, supplies a normal operation command corresponding to the access request and the bank addresses to the memory device, and causes the memory cores within normal access target banks selected by the bank addresses to execute normal operation,   the sequencer, in response to the access request, supplying, to the memory device, refresh bank information specifying banks other than the normal access target banks, and refresh burst length designating the number of times that refresh operation is performed, along with a background refresh command, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to successively execute the refresh operation a number of times corresponding to the refresh burst length.   
     
     
         21 . The memory controller according to  claim 20 , wherein the sequencer determines whether the background refresh command can be issued or not, on the basis of information indicating an access target data area in response to the access request, and, if the background refresh command can be issued, obtains the refresh bank information and the refresh burst length on the basis of the information indicating an access target data area. 
     
     
         22 . The memory controller according to  claim 21 , further comprising a register in which are set memory map information for associating two-dimensionally arrayed data with a memory space, and bank number information for executing the refresh operation corresponding to the background refresh command, wherein
 the sequencer obtains the refresh bank information and the refresh burst length on the basis of the information indicating an access target data area and the set information of the register.   
     
     
         23 . A memory system, comprising:
 a memory controller; and   a memory device which is operated in response to a command from the memory controller, wherein   the memory device has a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses,   each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and   the memory device further has a control circuit which causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.   
     
     
         24 . The memory system according to  claim 23 , wherein, during a period of rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the control circuit causes the memory cores within the banks selected by the bank addresses and within banks adjacent to the selected banks, to execute the normal memory operation in response to the normal operation command, and prohibits the refresh operation during the normal memory operation. 
     
     
         25 . A memory controller which controls a memory device having: a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cores within the plurality of banks, wherein
 each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of whose a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and   the memory controller has a sequencer which, in response to an access request from a host device, determines that the access request is for horizontal access in which the two-dimensionally arrayed data is accessed in a horizontal direction, supplies a normal operation command corresponding to the horizontal access and the bank addresses to the memory device, and causes the memory cores within horizontal access target banks selected by the bank addresses to execute normal operation,   the sequencer, in response to the access request, supplying refresh bank information for specifying banks other than the horizontal access target banks, and a background refresh command to the memory device, and, during the normal operation, causing the memory cores within refresh target banks related to the refresh bank information to execute the refresh operation.   
     
     
         26 . The memory controller according to  claim 25 , wherein when the access request is for rectangular access in which an arbitrary rectangular area of the two-dimensionally arrayed data is accessed, the sequencer supplies a normal operation command corresponding to the rectangular access and the bank addresses to the memory device, and causes the memory cores within access target banks selected by the bank addresses to execute normal operation, but does not issue the background refresh command during the normal memory operation.