Field effect transistor, compound semiconductor substrate and process for forming a recess therein

Abstract

A III-V field effect transistor comprising a semiconductor channel layer having an electrically conducting channel; an ohmic contact layer on the semiconductor channel layer, the ohmic contact layer having a recess structure disposed therethrough to the semiconductor channel layer; the bottom of the ohmic contact layer comprising an etch stop layer comprising Aluminium and Phosphorous and defining the shape of the recess at its junction with the semiconductor channel layer.

1 .- 36 . (canceled) 
   
   
       37 . A process for forming a recess in a semiconductor substrate including a semiconductor channel layer having an electrically conducting channel, an ohmic contact layer on the semiconductor channel layer, and an etch stop layer sandwiched between the ohmic contact layer and semiconductor channel layer, said process comprising the steps of:
 covering part of the ohmic contact layer in a masking material;   forming at least one recess in the ohmic contact layer by etching the area not covered in the masking material, where the depth of the recess is determined by the etch stop layer; and   further etching through the etch stop layer.   
   
   
       38 . A process as claimed in  claim 37 , wherein the etching of the recess is carried out with a dry etch chemistry. 
   
   
       39 . A process as claimed in  claim 38 , wherein the dry etch chemistry comprises a mixture of fluorine and chlorine. 
   
   
       40 . A process as claimed in  claim 37 , wherein the etching of the recess is carried out with a wet etch chemistry. 
   
   
       41 . A process as claimed in  claim 40 , wherein the wet etch chemistry comprises a mixture of hydrogen peroxide and a dilute acid or base. 
   
   
       42 . A process as claimed in  claim 40 , wherein the wet etch chemistry comprises a mixture of hydrogen peroxide and dilute sulphuric acid. 
   
   
       43 . A process as claimed in  claim 40 , wherein the wet etch chemistry comprises a mixture of hydrogen peroxide and dilute hydrofluoric acid. 
   
   
       44 . A process as claimed in  claim 40 , wherein the wet etch chemistry comprises hydrogen peroxide and dilute ammonia. 
   
   
       45 . A process as claimed in  claim 44 , wherein the masking material is a resist. 
   
   
       46 . A process as claimed in  claim 45 , wherein the resist is a photoresist. 
   
   
       47 . A process as set forth in  claim 37 , wherein the etch stop layer comprises aluminum and phosphorous.