Multi-path redundant architecture for fault tolerant fully buffered dimms

Abstract

The present invention is directed to a multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs). The architecture includes: a FB-DIMM channel including a plurality of DIMM modules and a memory controller; a bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order

1 . A multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs), comprising:
 a FB-DIMM channel including a plurality of DIMM modules and a memory controller;   a bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and   a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order.   
   
   
       2 . The architecture of  claim 1 , wherein the first and second bi-directional serial memory busses use single-ended signaling. 
   
   
       3 . The architecture of  claim 1 , wherein the second connection order is opposite that of the first connection order. 
   
   
       4 . The architecture of  claim 1 , wherein the bidirectional serial memory bus couples the memory controller to the first DIMM module in the FB-DIMM channel, and wherein the redundant bidirectional serial memory bus couples the memory controller to the last DIMM module in channel in the FB-DIMM channel. 
   
   
       5 . A memory system, comprising:
 a fault tolerant fully buffered dual inline memory module (FB-DIMM) channel including a plurality of DIMM modules and a memory controller;   a bi-directional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and   a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order.   
   
   
       6 . The memory system of  claim 5 , wherein the first and second bidirectional serial memory busses use single-ended signaling. 
   
   
       7 . The memory system of  claim 5 , wherein the second connection order is opposite that of the first connection order. 
   
   
       8 . The memory system of  claim 5 , wherein the bidirectional serial memory bus couples the memory controller to the first DIMM module in the FB-DIMM channel, and wherein the redundant bi-directional serial memory bus couples the memory controller to the last DIMM module in channel in the FB-DIMM channel.