US2008157367A1PendingUtilityA1

Multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same

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Assignee: KIM SOO HYUNPriority: Dec 28, 2006Filed: May 30, 2007Published: Jul 3, 2008
Est. expiryDec 28, 2026(~0.5 yrs left)· nominal 20-yr term from priority
Inventors:Soo Hyun KimBaek Mann KimYoung Jin LeeDong Ha JungJeong-Tae Kim
H10P 14/432H10P 14/43H10W 20/425H10W 20/048H10W 20/035H10W 20/033H10D 64/011H10P 14/40
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Claims

Abstract

A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

Claims

exact text as granted — not AI-modified
1 . A multi-layer metal wiring of a semiconductor device comprising:
 a lower Cu wiring;   an upper Al wiring formed over the lower Cu wiring and electrically contacting the lower Cu wiring; and   a W-based diffusion barrier layer formed between the lower Cu wiring and the upper Al wiring.   
   
   
       2 . The multi-layer metal wiring of the semiconductor according to  claim 1 , wherein the W-based diffusion barrier layer comprises a WN layer. 
   
   
       3 . The multi-layer metal wiring of the semiconductor according to  claim 2 , wherein the WN layer has a thickness of 50 to 200 Å. 
   
   
       4 . The multi-layer metal wiring of the semiconductor according to  claim 1 , wherein the W-based diffusion barrier layer comprises a stacked layer of a W layer and a WN layer. 
   
   
       5 . The multi-layer metal wiring of the semiconductor according to  claim 4 , wherein the stacked layer of the W layer and the WN layer has a thickness of 50 to 300 Å. 
   
   
       6 . The multi-layer metal wiring of the semiconductor according to  claim 1 , wherein the W-based diffusion barrier layer comprises a WSiNy layer. 
   
   
       7 . The multi-layer metal wiring of the semiconductor according to  claim 6 , wherein the WSiNy layer has a thickness of 50 to 200 Å. 
   
   
       8 . The multi-layer metal wiring of the semiconductor according to  claim 1 , wherein the W-based diffusion barrier layer comprises a stacked layer of a WSix layer and a WSixNy layer. 
   
   
       9 . The multi-layer metal wiring of the semiconductor according to  claim 8 , wherein the stacked layer of the WSix layer and the WSixNy layer has a thickness of 50 to 300 Å. 
   
   
       10 . The multi-layer metal wiring of the semiconductor according to  claim 1 , wherein the upper Al wiring comprises an Al nucleation growth layer formed on the diffusion barrier layer. 
   
   
       11 . The multi-layer metal wiring of the semiconductor according to  claim 10 , wherein the Al nucleation growth layer has a thickness of 50 to 500 Å. 
   
   
       12 . A method for forming a multi-layer metal wiring of a semiconductor device including:
 forming a lower Cu wiring over a semiconductor substrate;   forming a w-based diffusion barrier layer on the lower Cu wiring; and forming an upper Al wiring over the lower Cu wiring including the W-based diffusion barrier layer.   
   
   
       13 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12 , wherein the W-based diffusion barrier layer comprises a WN layer. 
   
   
       14 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 13 , wherein the WN layer has a thickness of 50 to 200 Å. 
   
   
       15 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 13 , wherein the WN layer is formed in an ALD or CVD method. 
   
   
       16 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 13 , wherein the WN layer is formed under a temperature in the range of 200 to 400° C. and a pressure in the range of 1 to 40 Torr. 
   
   
       17 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12 , wherein the W-based diffusion barrier layer comprises a stacked layer of a W layer and a WN layer. 
   
   
       18 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 17 , wherein the stacked layer of the W layer and the WN layer has a thickness of 50 to 300 Å. 
   
   
       19 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 17 , wherein the stacked layer of the W layer and the WN layer is formed by depositing the W layer and nitrifying the surface of the W layer. 
   
   
       20 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 17 , wherein the W layer is deposited in an ALD or CVD method. 
   
   
       21 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 17 , wherein the W layer is deposited under a temperature in the range of 200 to 400° C. and a pressure in the range of 1 to 40 Torr. 
   
   
       22 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 19 , wherein the nitrification on the surface of the W layer is performed by a heat treatment or a plasma treatment under the atmosphere of any one of NH 3 , N 2 H 4 , N 2 , and N 2 /H 2 . 
   
   
       23 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12 , wherein the W-based layer is formed of a WSiNy layer. 
   
   
       24 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 23 , wherein the WSiNy layer has a thickness of 50 to 200 Å. 
   
   
       25 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 23 , wherein the WSiNy layer is formed in an ALD or CVD method. 
   
   
       26 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 23 , wherein the WSiNy layer is formed under a temperature in the range of 300 to 500° C. and a pressure in the range of 0.01 to 10 Torr. 
   
   
       27 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12 , wherein the W-based diffusion barrier layer comprises a stacked layer of a WSix layer and a WSiNy layer. 
   
   
       28 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 27 , wherein the stacked layer of the WSix layer and the WSiNy layer has a thickness of 50 to 300 Å. 
   
   
       29 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 27 , wherein the stacked layer of the WSix layer and the WSiNy layer is formed by depositing the WSix layer and nitrifying the surface of the WSix layer. 
   
   
       30 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 27 , wherein the WSix layer is deposited in an ALD or CVD method. 
   
   
       31 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 29 , wherein the WSix layer is deposited under a temperature in the range of 300 to 500° C. and a pressure in the range of 0.01 to 10 Torr. 
   
   
       32 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 29 , wherein the nitrification on the surface of the WSix layer is performed by a heat treatment or a plasma treatment under the atmosphere of any one of NH 3 , N 2 H 4 , N 2 , and N 2 /H 2 . 
   
   
       33 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12  further comprising forming a Al nucleation growth layer on the diffusion barrier layer prior to forming the upper Al wiring. 
   
   
       34 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 33 , wherein the Al nucleation growth layer has a thickness of 50 to 500 Å based on a CVD method. 
   
   
       35 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12  comprising:
 the method for forming the upper Al wiring includes the steps of depositing the Al layer over the diffusion barrier layer based on a PVD method at a temperature in the range of 200 to 400° C.; and   performing a heat treatment on the Al layer at a temperature in the range of 400 to 500° C.   
   
   
       36 . The method for forming the multi-layer metal wiring of the semiconductor device according to  claim 12  further comprising:
 depositing a first Al layer over the diffusion barrier layer in a PVD method at a temperature in the range of 150 to 200° C.; and   depositing a second Al layer over the first Al layer in a PVD method at a temperature in the range of 200 to 450° C.

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