Efficient power management techniques for computer systems

Abstract

Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a control module. The interface communicates with the processor regarding power states of the processor. The control module may initiate draining the IOQ upon a commencement of a power state transition for the processor. The control module allows the transition of the processor to continue during the draining of the IOQ. However, at a particular point in the transition, the control module may determine whether the IOQ is empty. If so, then the control module may allow the transition of the processor to continue. Otherwise, the control module may stop the transition of the processor until the IOQ is empty.

1 . An apparatus, comprising:
 an input output queue (IOQ); and   an interface coupled to a processor, the interface to provide for communication with the processor regarding power management activities of the processor;   a control module to initiate an IOQ draining process upon commencement of a power state transition for the processor, the transition from a first power state to a second lower power state;   wherein the control module to provide for the transition of the processor from the first power state to the second lower power state to continue during the draining of the IOQ.   
   
   
       2 . The apparatus of  claim 1 , wherein the second lower power state is a C 5  state. 
   
   
       3 . The apparatus of  claim 2 , wherein the control module is to:
 at a time prior to entry into a C 3  state, determine whether the IOQ is empty;   allow the transition of the processor to continue when the control module determines that the IOQ is empty; and   otherwise pause the transition of the processor until the IOQ is empty.   
   
   
       4 . The apparatus of  claim 3 , wherein the first state is a C 0  state. 
   
   
       5 . The apparatus of  claim 1 , wherein the control module is to disable snoops associated with the IOQ upon commencement of the power state transition for the processor 
   
   
       6 . The apparatus of  claim 1 , wherein the control module is to receive an input/output (I/O) read from the processor, the I/O read indicating commencement of the power state transition of for the processor. 
   
   
       7 . The apparatus of  claim 1 , wherein the interface includes one or more sideband signal lines. 
   
   
       8 . A method, comprising:
 initiating an IOQ draining process upon commencement of a power state transition for the processor, the transition from a first power state to a second lower power state; and   allowing the transition of the processor from the first power state to the second lower power state to continue during the draining of the IOQ.   
   
   
       9 . The method of  claim 8 , wherein the second power control state is a C 5  state. 
   
   
       10 . The method of  claim 9 , further comprising:
 at a time prior to entry into a C 3  state, allowing the transition of the processor to continue upon a determination that the IOQ is empty; and   otherwise pausing the transition of the processor until the IOQ is empty.   
   
   
       11 . The method of  claim 10 , wherein the first power control state is a C 0  state. 
   
   
       12 . The method of  claim 8 , further comprising:
 disabling snoops associated with the IOQ upon commencement of the power state transition for the processor   
   
   
       13 . The method of  claim 8 , further comprising:
 receiving an input/output (I/O) read from the processor, the I/O read indicating commencement of the power state transition of for the processor.   
   
   
       14 . A system, comprising:
 a processor;   a chipset, the chipset including
 an input output queue (IOQ); and 
 a control module to initiate an IOQ draining process upon commencement of a power state transition for the processor, the transition from a first power state to a second lower power state; 
 wherein the control module to provide for the transition of the processor from the first power state to the second lower power state to continue during the draining of the IOQ. 
   
   
   
       15 . The system of  claim 14 , further comprising an interface coupled to the processor, the interface to provide for communication with the processor regarding power management states of the processor. 
   
   
       16 . The system of  claim 15 , wherein the interface includes one or more sideband signal lines. 
   
   
       17 . The system of  claim 14 , wherein the control module is to:
 at a time prior to entry into a C 3  state, determine whether the IOQ is empty;   allow the transition of the processor to continue when the control module determines that the IOQ is empty; and   otherwise pause the transition of the processor until the IOQ is empty.   
   
   
       18 . The system of  claim 14 , wherein the first power state is a C 0  state, and the second lower power state is a C 5  state. 
   
   
       19 . The system of  claim 14 , further comprising one or more memory devices coupled to the chipset. 
   
   
       20 . The system of  claim 19 , wherein the one or more memory devices comprise random access memory (RAM).