Nand flash memory having c/a pin and flash memory system including the same

Abstract

A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.

1 . A NAND flash memory comprising:
 a memory cell array storing data;   a command/address pin through which a command and an address are received for transmitting data; and   a data input/output pin through which data are transmitted in the memory cell array.   
   
   
       2 . The NAND flash memory of  claim 1 , further comprising a status register receiving a status read command through the command/address pin and providing an operational status of the NAND flash memory to a flash controller. 
   
   
       3 . The NAND flash memory of  claim 2 , wherein the flash controller sends the status read command to the NAND flash memory. 
   
   
       4 . The NAND flash memory of  claim 2 , wherein the status register sends a status signal SQ to the flash controller to inform the flash controller whether the NAND flash memory is internally operational. 
   
   
       5 . The NAND flash memory of  claim 4 , wherein the flash controller controls the internal operation of the NAND flash memory in response to the status signal SQ. 
   
   
       6 . The NAND flash memory of  claim 1 , wherein the data transmitted through the data input/output pin is transmitted according to a toggling of a data strobe signal DQS. 
   
   
       7 . The NAND flash memory of  claim 6 , wherein the data transmitted through the data input/output pin is transmitted by a DDR (double data rate) transmission method. 
   
   
       8 . The NAND flash memory of  claim 1 , further comprising a command/address buffer receiving the command and address received through command/address pin. 
   
   
       9 . The NAND flash memory of  claim 8 , further comprising a control unit controlling the reception of the command and address. 
   
   
       10 . The NAND flash memory of  claim 9 , wherein the control unit receives a chip enable signal nCE and a load signal nLOAD from a flash controller and controls the reception of the command and address. 
   
   
       11 . A flash memory system comprising:
 a flash controller, and   a flash memory module comprising a plurality of NAND flash memories,   wherein each of the NAND flash memories comprises:   a memory cell array storing data;   a command/address pin through which a command and an address are received from the flash controller for transmitting data in the memory cell array; and   a data input/output, pin through which data is transmitted in the memory cell array.   
   
   
       12 . The flash memory system of  claim 11 , wherein each of the NAND flash memories further comprises a status register receiving a status read command through the command/address pin and providing an operational status of the NAND flash memory to the flash controller. 
   
   
       13 . The flash memory system of  claim 12 , wherein the flash controller sends the status read command to the NAND flash memory. 
   
   
       14 . The flash memory system of  claim 12 , wherein the status register sends a status signal SQ to the flash controller to inform the flash controller whether the NAND flash memory is internally operational. 
   
   
       15 . The flash memory system of  claim 14 , wherein the flash controller controls the internal operation of the NAND flash memory in response to the status signal SQ. 
   
   
       16 . The flash memory system of  claim 11 , wherein the data transmitted through the data input/output pin is transmitted according to a toggling of a data strobe signal DQS. 
   
   
       17 . The flash memory system of  claim 16 , wherein the data transmitted through the data input/output pin is transmitted by a DDR (double data rate) transmission method. 
   
   
       18 . The flash memory system of  claim 1 , wherein each of the NAND flash memories further comprises a command/address buffer receiving the command and address received through command/address pin. 
   
   
       19 . The flash memory system of  claim 18 , wherein each of the NAND flash memories further comprises a control unit controlling the reception of the command and address. 
   
   
       20 . The flash memory system of  claim 19 , wherein the control unit receives a chip enable signal nCE and a load signal nLOAD from the flash controller and controls the reception of the command and address.