Wear leveling techniques for flash eeprom systems

Abstract

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

1 . A method of operating a memory system having a non-volatile array of memory cells with a controller thereof connected thereto, wherein the array of memory cells is divided into distinct groups of memory cells that are erasable together prior to re-writing data therein, wherein:
 a plurality of quantities of a characteristic of operation of the array of memory cells is monitored,   a variable related to differences in the monitored quantities is feed back to the controller, and   the controller uses the feedback variable to change the characteristic of operation in a manner to reduce the feed back variable during further operation of the memory system but with a feedback gain that is limited by only changing the characteristic of operation at intervals defined by a total of the quantities of the characteristic.   
   
   
       2 . The method of  claim 1 , wherein the characteristic includes operational cycles experienced by individual groups of memory cells, and the quantities include numbers of the operational cycles experienced by the individual groups of memory cells. 
   
   
       3 . The method of  claim 2 , wherein the feedback variable includes a difference between the numbers of operational cycles of individual groups of memory cells. 
   
   
       4 . The method of  claim 3 , wherein the controller controls the numbers of operational cycles experienced by the individual groups of memory cells in a manner that tends to minimize the differences between the numbers of operational cycles of individual groups of memory cells. 
   
   
       5 . The method of  claim 4 , wherein the controller controls the numbers of operational cycles experienced by the individual groups of memory cells by at least moving data stored in individual groups of memory cells among identified groups of memory cells and reassigning logical addresses of the identified groups of memory cells that are recognized at an interface of the memory system to physical addresses of different identified groups of memory cells.