Integrated complementary low voltage rf-ldmos

Abstract

Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode.

1 . A lateral double diffused metal oxide semiconductor (LDMOS) transistor comprising:
 a) a gate oxide having a plurality of thicknesses under a gate electrode;   b) a source tap region of a first conductivity type;   c) a lateral source spacer of a second conductivity type lying substantially between a first edge of said gate electrode and said source tap, said first conductivity type being opposite to said second conductivity type;   d) a drain region of said second conductivity type on an opposite side of said gate electrode; and   e) at least one buffer region of that at least partially surrounds said drain region and which extends under a second edge of said gate electrode.   
   
   
       2 . The LDMOS transistor set forth in  claim 1  wherein said plurality of thicknesses of said gate oxide is two. 
   
   
       3 . The LDMOS transistor set forth in  claim 2  wherein a thinner gate oxide is under said first edge of said gate electrode and a thicker gate oxide is under a second edge of said gate electrode. 
   
   
       4 . The LDMOS transistor set forth in  claim 3  wherein said at least one buffer region extends laterally to below said thicker gate oxide. 
   
   
       5 . The LDMOS transistor set forth in  claim 1  wherein said at least one buffer region comprises two buffer regions, a first buffer region of said second conductivity type lying below said drain region and above a second buffer region of said second conductivity type. 
   
   
       6 . The LDMOS transistor set forth in  claim 5  wherein said drain region is of a higher dopant concentration than said first buffer region which, in turn, has a higher dopant concentration than said second buffer region. 
   
   
       7 . The LDMOS transistor set forth in  claim 1  further including a body of said first conductivity type which lies below at least a portion of said source tap region and under said lateral source spacer and extends to said gate oxide. 
   
   
       8 . The LDMOS transistor set forth in  claim 7  wherein said body is of a lower dopant concentration than said source tap region. 
   
   
       9 . The LDMOS transistor set forth in  claim 7  further including a well of said first conductivity type under a least a portion of said body. 
   
   
       10 . The LDMOS transistor set forth in  claim 9  further including a first buried layer of said first conductivity type extending from said well towards a substrate. 
   
   
       11 . The LDMOS transistor set forth in  claim 1  further including a substrate laying below said gate electrode, said gate oxide, said source tap region, said lateral source spacer, said drain region and said at least one buffer region. 
   
   
       12 . The LDMOS transistor set forth in  claim 11  wherein said substrate is of said second conductivity type. 
   
   
       13 . The LDMOS transistor set forth in  claim 11  wherein said substrate is of said first conductivity type. 
   
   
       14 . The LDMOS transistor set forth in  claim 11  further including an epi layer lying on said substrate. 
   
   
       15 . The LDMOS transistor set forth in  claim 14  further including a well of said first conductive type lying on said epi layer. 
   
   
       16 . The LDMOS transistor set forth in  claim 3  wherein said at least one buffer region comprises two buffer regions, a first buffer region of said second conductivity type lying below said drain region and above a second buffer region of said first conductivity type. 
   
   
       17 . The LDMOS transistor set forth in  claim 16  wherein said second buffer region extends latterly and deeply under all of the thick section and part of the thin section of the split gate oxide to overlap the body region. 
   
   
       18 . The LDMOS transistor set forth in  claim 1  wherein said at least one buffer region consists of a single buffer region. 
   
   
       19 . The LDMOS transistor set forth in  claim 14  further including a buried layer lying on said epi layer. 
   
   
       20 . The LDMOS transistor set forth in  claim 14  further including a buried layer of said first conductivity type lying on said epi layer. 
   
   
       21 . The LDMOS transistor set forth in  claim 20  further including a buried layer of said second conductivity type lying on said buried layer of said first conductivity type. 
   
   
       22 . The LDMOS transistor set forth in  claim 1  farther including an isolation ring surrounding said transistor. 
   
   
       23 . The LDMOS transistor set forth in  claim 22  wherein said isolation ring is connected to a region in said transistor which is the same conductivity type as said isolation ring. 
   
   
       24 . A high frequency lateral double diffused metal oxide semiconductor (LDMOS) transistor comprising:
 a) a gate oxide having a thinner section under a first edge of a gate electrode and a thicker section under a second edge of said gate electrode;   b) a lateral source spacer of a second conductivity type lying between said first edge of said gate electrode;   c) a source tap region of a first conductivity type, said first conductivity type being opposite to said second conductivity type;   d) a drain region of said second conductivity type;   e) a first buffer region of said second conductivity type lying below said drain region and above a second buffer region of said second conductivity type, both of which at least partially surround said drain region and which extend under said second edge of said gate electrode, said drain region is of a higher dopant concentration than said first buffer region which, in turn, has a higher dopant concentration than said second buffer region;   f) a body of said second conductivity type which lies below at least a portion of said source tap region and under said lateral source spacer and extends to said gate oxide, said body being of a lower dopant concentration than said source tap region;   g) a well of said first conductivity type under a least a portion of said body;   h) a buried layer of said first conductivity type extending from said well towards a substrate; and   i) a substrate laying below said gate electrode, said gate electrode, said spacer, said source region, said drain region, said first and second buffer regions, said body, said well, and said buried layer; and   j) an epi layer of said first conductivity type lying on said substrate.   
   
   
       25 . A method of making a LDMOS transistor comprising the steps of:
 a) growing an epi layer on a substrate;   b) forming a gate electrode on a split gate oxide formed on said epi layer;   c) forming a body of said first conductivity type and a source spacer of said second conductivity type which are self-aligned to first side of said polysilicon gate electrode; said second conductivity type being opposite to said first conductivity type;   d) forming a first buffer layer of said second conductivity type self-aligned to a second edge of said polysilicon gate electrode;   e) forming first and second side wall oxides on said first edge and said second edge, respectively, of said polysilicon gate electrode; and   f) forming a first drain region of said second conductivity type self-aligned to said second side wall oxide   g) forming a source tap layer of said first conductivity type self-aligned to said first side wall oxide such that said source tap layer and said body overlap in a region spaced away from said first edge of said gate electrode, said source spacer region extending from said source tap layer to under at least said first edge of said polysilicon gate electrode.   
   
   
       26 . The method set forth in  claim 25  further including the step of forming a well of said first conductivity type under a least a portion of said body. 
   
   
       27 . The method set forth in  claim 26  further including the step of forming a first buried layer of said first conductivity type extending from said well towards a substrate. 
   
   
       28 . The method set forth in  claim 25  wherein said substrate is of said first conductivity type. 
   
   
       29 . The method set forth in  claim 25  wherein said substrate is of said second conductivity type. 
   
   
       30 . The method set forth in  claim 25  further including the step of forming a second buffer layer of said second conductivity type self-aligned to a second edge of said polysilicon gate electrode and lying below said first buffer. 
   
   
       31 . The method set forth in  claim 30  wherein the steps of forming said first buffer layer, said drain region, and said second buffer layer includes forming said drain layer with a higher dopant concentration than said first buffer layer which, in turn, is formed with a higher dopant concentration than said second buffer layer. 
   
   
       32 . The method set forth in  claim 25  further including the step of forming a well of said second conductive type lying on said epi layer. 
   
   
       33 . The method set forth in  claim 25  further including the step of forming a second buffer layer of said first conductivity type self-aligned to a second edge of said polysilicon gate electrode and lying below said first buffer. 
   
   
       34 . The method set forth in  claim 33  wherein said second buffer region extends latterly and deeply under all of the thick section and part of the thin section of the split gate oxide to overlap the body region. 
   
   
       35 . The method set forth in  claim 25  further including the step of forming a buried layer lying on said epi layer. 
   
   
       36 . The method set forth in  claim 25  further including the step of forming a buried layer of said first conductivity type lying on said epi layer. 
   
   
       37 . The method set forth in claim.  36  further including the step of forming a buried layer of said second conductivity type lying on said buried layer of said first conductivity type. 
   
   
       38 . The method set forth in  claim 25  further including the step of forming an isolation ring surrounding said transistor. 
   
   
       39 . The method set forth in  claim 38  wherein said isolation ring is connected to a region in said transistor which is the same conductivity type as said isolation ring.