Novel context instruction cache architecture for a digital signal processor

Abstract

Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

1 . A method for reducing cache thrashing in a digital signal processor (DSP), comprising:
 dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program; and   dynamically disabling the caching of the instructions upon encountering an exit point in the frequently executed instructions.   
     
     
         2 . The method of  claim 1 , further comprising:
 dynamically identifying the current frequently executed instructions during run-time of the program.   
     
     
         3 . The method of  claim 2 , further comprising:
 holding the current frequently executed instructions in instruction cache memory until identifying and enabling caching of the instructions in next frequently executed instructions.   
     
     
         4 . The method of  claim 1 , wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump. 
     
     
         5 . The method of  claim 1 , wherein disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions comprises:
 incrementing an N-bit up-counter upon caching each of the instructions associated with the current frequently executed instructions into the instruction cache memory, wherein the N-bit up-counter has a number of states equal to number of entries available in the instruction cache memory; and   dynamically disabling the caching of the instructions associated with the current frequently executed instructions into the instruction cache memory upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter.   
     
     
         6 . The method of  claim 1 , further comprising:
 dynamically re-enabling caching of instructions upon encountering next frequently execute instructions.   
     
     
         7 . An article comprising:
 a storage medium having instructions, that when executed by a computing platform, result in execution of a method for reducing cache thrashing comprising:
 dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program; and 
 dynamically disabling the caching of the instructions upon encountering an exit point in the frequently executed instructions. 
   
     
     
         8 . The article of  claim 7 , further comprising:
 dynamically identifying the current frequently executed instructions during run-time.   
     
     
         9 . The article of  claim 8 , further comprising:
 holding the instructions in instruction cache memory until identifying a next frequently executed instructions and enabling caching of the instructions in the next frequently executed instructions.   
     
     
         10 . The article of  claim 7 , wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump. 
     
     
         11 . The article of  claim 7 , wherein disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions comprises:
 incrementing an N-bit up-counter upon caching each of the instructions into the instruction cache memory, wherein the N-bit up-counter has a number of states equal to number of entries available in the instruction cache memory; and   dynamically disabling the caching of the instructions into the instruction cache memory upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter.   
     
     
         12 . A digital signal processor, comprising:
 an instruction cache memory; and   a computational unit coupled to the instruction cache memory to dynamically enable loading of instructions upon encountering frequently executed instructions in a program and to dynamically disable loading of instructions upon encountering an exit point associated with the frequently executed instructions.   
     
     
         13 . The digital signal processor of  claim 12 , wherein the computational unit comprises:
 an N-bit up-counter having a number of states that is equal to a predetermined number of entries in the instruction cache memory;   a decoder logic circuit that locates the current frequently executed instructions in the program;   a cache controller; and   an enabler/disabler logic circuit that enables caching of the instructions associated with the located current frequently executed instructions via the cache controller, wherein the N-bit up-counter increments upon storing each instruction in the instruction cache memory, and wherein the enabler/disabler circuit disables the caching of the instructions in the instruction cache memory via the cache controller upon the N-bit up-counter reaching a saturation point or upon encountering an exit point in the instructions associated with the frequently executed instructions before reaching the saturation point.   
     
     
         14 . The digital signal processor of  claim 13 , wherein the instruction cache memory has a predetermined number of entries, wherein the N-bit up-counter has a number of states that is equal to the predetermined number of entries in the internal cache memory, wherein the N-bit up-counter increments a counter value for each instruction stored in the instruction cache memory, and wherein the enabler/disabler logic circuit disables the storing of the instructions via the cache controller upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter. 
     
     
         15 . The digital signal processor of  claim 12 , wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump. 
     
     
         16 . A self-configuring cache architecture for a digital signal processor, comprising:
 cache memory;   an internal memory;   an external memory; and   a computational unit comprising:   an execution-space decode logic circuit that dynamically determines whether a current instruction in an executable program that is coming from an external memory or an internal memory; and   a cache control logic circuit that configures the cache memory to behave like a traditional cache or a conflict cache based on the outcome of the determination, wherein the cache control logic circuit transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory.   
     
     
         17 . The self-configuring cache architecture of  claim 16 , wherein the execution-space decode logic circuit determines, during run-time execution of the executable program, whether a instruction is coming from the external memory or the internal memory and then outputs an external execution-space control signal if the current instruction is coming from the external memory and outputs an internal execution-space control signal if the current instruction is coming from the internal memory. 
     
     
         18 . The self-configuring cache architecture of  claim 17 , wherein the cache control logic circuit comprises:
 a cache controller;   a conflict instruction cache enabler that determines whether the current instruction in the executable program has a memory conflict condition and then outputs a conflict instruction load enable signal upon finding the memory conflict condition;   a traditional instruction cache enabler that enables a traditional instruction load enable signal for the current instruction in the executable program upon receiving the current instruction from the external memory; and   a MUX coupled to the execution-space decode logic circuit, the conflict instruction cache enabler and the traditional instruction cache enabler outputs an instruction load enable signal via the cache controller to configure the cache memory to behave like a traditional cache or a conflict cache based on the instruction load enable signal, wherein the instruction load enable signal transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory.   
     
     
         19 . The self-configuring cache architecture of  claim 18 , wherein the MUX outputs the instruction load enable signal and enables the cache memory to behave like a conflict cache via the cache controller and transfers the current instruction to and between the internal memory, cache memory and the computational unit upon finding the memory conflict condition and receiving the internal execution-space control signal. 
     
     
         20 . The self-configuring cache architecture of  claim 19 , wherein the MUX outputs the instruction load enable signal and enables the cache memory to behave like a traditional cache via the cache controller and transfers the current instruction, coming from the external memory, to and between the cache memory and the computation unit upon receiving the current instruction from the external memory and the traditional instruction load enable signal from the traditional instruction cache enabler. 
     
     
         21 . A method for self configuring a cache memory in a digital signal processor, comprising:
 determining during run-time execution of a program whether a current instruction is coming from an external memory or an internal memory;   outputting an external execution-space control signal or an internal execution-space control signal based on the determination;   determining whether a fetch phase of the current instruction coincides with the memory access phase of a preceding load or store instruction on program memory bus;   if so, outputting a conflict instruction load enable signal so that the cache memory behaves like a conflict cache and stores the current instruction in the cache memory upon receiving the internal execution-space control signal; and   outputting a traditional instruction load enable signal so that the cache memory behaves like a traditional cache and then stores the current instruction in the cache memory upon receiving the external execution-space control signal.