Reduced electric field dmos using self-aligned trench isolation

Abstract

A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

1 . An electronic device comprising:
 a gate area having a gate oxide and a control gate; and   a shallow trench isolation feature formed proximate to the gate area and comprised of a trench-fill dielectric having a full field oxide thickness and an uppermost portion formed substantially parallel to and at a higher cross-sectional elevation than an active portion of the gate oxide, the shallow trench isolation feature being coupled to at least a portion of the control gate.   
   
   
       2 . The electronic device of  claim 1  wherein the device is characterized as lacking a gate wraparound. 
   
   
       3 . The electronic device of  claim 1  wherein the control gate is comprised of a first and a second polysilicon layer, the first polysilicon layer having a first face coupled to the gate oxide and a second face coupled to the second polysilicon layer. 
   
   
       4 . The electronic device of  claim 3  wherein the second face of the first polysilicon layer is substantially parallel to and at a lower cross-sectional elevation than the uppermost portion of the shallow trench isolation feature. 
   
   
       5 . The electronic device of  claim 1  wherein the shallow trench isolation feature is formed in a silicon layer of a silicon-on-insulator substrate. 
   
   
       6 . A semiconductor electronic device comprising:
 a transistor having a source, a drain, and a gate area, the gate area having a control gate and a gate oxide, the gate area being characterized in that a gate wraparound area is absent; and   a shallow trench isolation feature comprised of a trench-fill dielectric having a full-field oxide thickness, the full-field oxide thickness having an uppermost sidewall area of the trench-fill dielectric coupled to at least a portion of the control gate.   
   
   
       7 . The semiconductor electronic device of  claim 6  wherein the shallow trench isolation feature further comprises an uppermost portion formed substantially parallel to and at a higher cross-sectional elevation than an active portion of the gate oxide. 
   
   
       8 . The semiconductor electronic device of  claim 6  wherein the control gate is comprised of a first and a second polysilicon layer, the first polysilicon layer having a first face located proximate to the gate oxide and a second face located proximate to the second polysilicon layer. 
   
   
       9 . The semiconductor electronic device of  claim 8  wherein the second face of the first polysilicon layer is substantially parallel to and at a lower cross-sectional elevation than an uppermost portion of the shallow trench isolation feature. 
   
   
       10 . The semiconductor electronic device of  claim 6  wherein the shallow trench isolation feature is formed in an n-well. 
   
   
       11 . The semiconductor electronic device of  claim 6  wherein the shallow trench isolation feature is formed in a silicon layer of a silicon-on-insulator substrate. 
   
   
       12 . An MOS transistor comprising:
 a source, a drain, and a gate area, the gate area having a control gate, a gate oxide, and characterized such that a gate wraparound area is absent; and   a shallow trench isolation feature comprised of a trench-fill dielectric having a full-field oxide thickness, the full-field oxide thickness having an uppermost sidewall area of the trench-fill dielectric coupled to at least a portion of the control gate layer, the shallow trench isolation feature further having an uppermost portion formed substantially parallel to and at a higher cross-sectional elevation than an active portion of the gate oxide.   
   
   
       13 . The MOS transistor of  claim 12  wherein the transistor has a double-diffused dopant region. 
   
   
       14 . The MOS transistor of  claim 12  wherein the control gate is comprised of a first and a second polysilicon layer, the first polysilicon layer having a first face located proximate to the gate oxide and a second face located proximate to the second polysilicon layer. 
   
   
       15 . The MOS transistor of  claim 14  wherein the second face of the first polysilicon layer is substantially parallel to and at a lower cross-sectional elevation than an uppermost portion of the shallow trench isolation feature. 
   
   
       16 . The MOS transistor of  claim 12  wherein the shallow trench isolation feature is formed in an n-well. 
   
   
       17 . The MOS transistor of  claim 12  wherein the shallow trench isolation feature is formed in a silicon layer of a silicon-on-insulator substrate. 
   
   
       18 . The MOS transistor of  claim 12  wherein a lowermost portion of the gate oxide is configured to be at least partially in electrical communication with a threshold enhancing dopant region.