US2008177855A1PendingUtilityA1

Packet communication apparatus

Assignee: RENESAS TECH CORPPriority: Sep 26, 2003Filed: Mar 21, 2008Published: Jul 24, 2008
Est. expirySep 26, 2023(expired)· nominal 20-yr term from priority
H04L 49/90H04L 69/162H04L 69/16H04L 69/22H04L 69/161
51
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Claims

Abstract

A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

Claims

exact text as granted — not AI-modified
1 . A packet communication apparatus comprising a CPU (Central Processing Unit), a memory, and a packet communication circuit, said packet communication apparatus acting as an interface between at least one network-connected controlled object and at least one network terminal that remotely monitors and controls the controlled object, said packet communication apparatus transmitting and receiving a packet between the controlled object and the network terminal,
 wherein said packet communication apparatus comprises communication middleware that causes said CPU to encapsulate data into a transmission packet and place the transmission packet in a work area in said memory,   wherein said packet communication apparatus further comprises a copy and operation unit that copies the transmission packet placed in the work area to a descriptor in said memory and, at the same time, executes a predetermined operation for the transmission packet, and   wherein said packet communication circuit transmits the transmission packet, which is obtained via a unique device driver and is stored in the descriptor in said memory, to the controlled object or the network terminal.   
     
     
         2 - 17 . (canceled)

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