Highly reliable NAND flash memory using a five side enclosed floating gate storage elements

Abstract

A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty.

1 . A storage element of a memory comprising a floating gate over laying a tunnel oxide, two high voltage dielectric regions on the silicon surface, extending on either side of the tunnel oxide, having connect diffusions extending under the said high voltage dielectric, there by forming a channel region under the tunnel oxide, a floating gate deposed over the tunnel oxide, a control gate deposed over and on the sides of the floating gate, coupled to it by means of capacitive coupling, but separated from the floating gate by an inter-poly dielectric, such that the channel conductance is controlled by the potential on the floating gate. 
   
   
       2 . The storage element in  claim 1 , wherein the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric increase the coupling between the control gate and the floating gate across the inter-poly dielectric. 
   
   
       3 . The storage element in  claim 2 , wherein the increase coupling between the control gate and floating gate allow reduction of high voltages used for program and erase. 
   
   
       4 . The storage element in  claim 1 , wherein the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric protects the floating gate from external contaminants. 
   
   
       5 . The storage element in  claim 1 , where in the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric prevent potentials from adjacent cells and elements coupling to and impacting the potential of the floating gate. 
   
   
       6 . The storage element in  claim 1 , wherein the control gate over lays the connect diffusion, but is separated from it by the high voltage dielectric adjacent the tunnel oxide, there by increases the coupling between the control gate and the connect diffusion. 
   
   
       7 . The storage element in  claim 6 , wherein having increased coupling between the control gate and the connect diffusion enables generation of inhibit voltages for the write of selected data from lower programming voltages. 
   
   
       8 . A storage element having connect diffusions spaced away from a tunnel oxide by having two high voltage dielectric regions on either side of the tunnel oxide, a floating gate overlaying the tunnel oxide, a control gate deposed over and on the sides of the floating gate, the control gate on the sides of the floating gate overlaying the high voltage dielectric, there by forming three separate but serially connected channel regions between the connect diffusions comprising:
 i. a pair of side select gate channels under the high voltage oxide on either side of a floating gate, controlled by applied potential on the control gate over laying the high voltage dielectric on either sides of the floating gate; and   ii. a floating gate channel under the tunnel oxide, that is controlled by a potential on the floating gate.   
   
   
       9 . The storage element in  claim 8 , wherein the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric increase the coupling between the control gate and the floating gate across the inter-poly dielectric. 
   
   
       10 . The storage element in  claim 9 , wherein the increase coupling between the control gate and floating gate allow reduction of high voltages used for program and erase. 
   
   
       11 . The storage element in  claim 8 , wherein the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric protects the floating gate from external contaminants. 
   
   
       12 . The storage element in  claim 8 , where in the control gate deposed over and on the sides of the floating gate but separated from it by the inter-poly dielectric prevent potentials from adjacent cells and elements coupling to and impacting the potential of the floating gate. 
   
   
       13 . The storage element in  claim 8 , wherein the control gate over lays the channel of the side select gate channels, but is separated from it by the high voltage dielectric adjacent the tunnel oxide, increases the coupling between the control gate and the channel 
   
   
       14 . The storage element in  claim 13 , wherein having increased coupling between the control gate and the channel enables generation of inhibit voltages for the write of selected data from lower programming voltages. 
   
   
       15 . A storage element having a pair of connect diffusions on either side of a channel region, a floating gate overlaying the channel region, but separated from it by a tunnel oxide, having a control gate deposed over and on the sides of the floating gate, but separated from it by an inter-layer dielectric, a pair of high voltage dielectric deposed on either side of the tunnel oxide, such that the control gate on the sides of the floating gate overlay the high voltage dielectric, providing five sided coverage for the floating gate and improved capacitive coupling between the control gate and floating gate while isolating the control gate from the channel and the connect diffusions.