Chip package structure and method of fabricating the same

Abstract

A method of fabricating a chip package structure includes the steps of providing a metal thin plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts. A chip is then disposed on the metal thin plate and a plurality of bonding wires is formed to electrically connect the chip to the second protrusion part and connect the second protrusion part to the third protrusion parts. Next, an upper encapsulant and a lower encapsulant are formed on an upper surface and a lower surface of the metal thin plate, respectively. Thereafter, an etching mask is formed on the lower surface and exposes the connections among the protrusion parts. Finally, the metal thin plate is etched, such that the first protrusion part, the second protrusion part and the third protrusion parts form a die pad, a bus bar and leads of a lead frame, respectively.

What is claimed is: 
     
         1 . A method of fabricating a chip package structure, comprising:
 providing a metal thin plate comprising an upper surface and a lower surface, wherein the upper surface of the metal thin plate has a first protrusion part, a second protrusion part, and a plurality of third protrusion parts, the second protrusion part being sandwiched between the first protrusion part and the third protrusion parts, the first, the second, and the third protrusion parts being connected to one another;   providing a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;   adhering the back surface of the chip to the first protrusion part;   forming a plurality of first bonding wires and a plurality of second bonding wires, wherein the first bonding wires respectively connect the chip bonding pads and the second protrusion part, and the second bonding wires respectively connect the second protrusion part and the third protrusion parts;   forming an upper encapsulant encapsulating the upper surface of the metal thin plate, the chip, the first bonding wires and the second bonding wires;   forming an etching mask on the lower surface to expose the connections among the first, the second, and the third protrusion parts; and   etching the metal thin plate to an extent that the first, the second, and the third protrusion parts are electrically insulated, such that the first protrusion part constructs a die pad, the second protrusion part forms a bus bar, and the third protrusion parts form a plurality of leads.   
     
     
         2 . The method of fabricating the chip package structure of  claim 1 , further comprising forming a lower encapsulant filled among the die pad, the bus bar and the leads after the step of etching the metal thin plate is implemented. 
     
     
         3 . The method of fabricating the chip package structure of  claim 2 , wherein the lower encapsulant is coplanar with the etching mask. 
     
     
         4 . The method of fabricating the chip package structure of  claim 2 , wherein the lower encapsulant further encapsulates the etching mask. 
     
     
         5 . The method of fabricating the chip package structure of  claim 2 , further comprising removing the etching mask and then forming the lower encapsulant after the step of etching the metal thin plate is implemented. 
     
     
         6 . The method of fabricating the chip package structure of  claim 1 , wherein the metal thin plate is a copper foil. 
     
     
         7 . The method of fabricating the chip package structure of  claim 1 , wherein the first bonding wires and the second bonding wires are formed through a wire bonding technique. 
     
     
         8 . The method of fabricating the chip package structure of  claim 1 , wherein the etching mask is a patterned photoresist layer or a patterned solder mask layer. 
     
     
         9 . The method of fabricating the chip package structure of  claim 1 , wherein one of the first protrusion part, the second protrusion part and the third protrusion parts or a combination thereof has a down-set design. 
     
     
         10 . A chip package structure, comprising:
 a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;   a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising:
 a die pad to which the back surface of the chip is adhered; 
 a plurality of leads surrounding the die pad; and 
 at least a bus bar disposed between the die pad and the leads; 
   a plurality of first bonding wires connected to the chip bonding pads and to the bus bar, respectively;   a plurality of second bonding wires connected to the bus bar and to the leads, respectively; and   an upper encapsulant encapsulating the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires.   
     
     
         11 . The chip package structure of  claim 10 , further comprising an etching mask disposed on the lower surface of the lead frame. 
     
     
         12 . The chip package structure of  claim 11 , further comprising a lower encapsulant filled among the die pad, the bus bar and the leads. 
     
     
         13 . The chip package structure of  claim 12 , wherein the lower encapsulant further encapsulates the etching mask. 
     
     
         14 . The chip package structure of  claim 10 , further comprising an etching mask disposed on the lower surface of the bus bar and the lower surface of the leads. 
     
     
         15 . The chip package structure of  claim 14 , further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the die pad. 
     
     
         16 . The chip package structure of  claim 10 , further comprising an etching mask disposed on the lower surface of the die pad and the lower surface of the bus bar. 
     
     
         17 . The chip package structure of  claim 16 , further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the leads. 
     
     
         18 . The chip package structure of  claim 10 , further comprising an etching mask disposed on the lower surface of the bus bar. 
     
     
         19 . The chip package structure of  claim 18 , further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the die pad and the lower surface of the leads. 
     
     
         20 . The chip package structure of  claim 10 , further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to encapsulate the lower surface of the lead frame. 
     
     
         21 . The chip package structure of  claim 10 , wherein one of the bus bar, the die pad and the leads or a combination thereof has a down-set design.