Passive electronic device
Abstract
A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.
Claims
exact text as granted — not AI-modified1 . An interposer comprising:
a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising:
a plurality of parallel plates with a dielectric there between;
at least one first external termination in electrical contact with a first set of alternate parallel plates; and
at least one second external termination in electrical contact with a second set of alternate parallel plates;
said capacitor is electrically or physically connected to said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection; and at least one upper connection, said first external termination and said second external termination arranged for direct electrical contact with element contact pads of a common element.
2 . The interposer of claim 1 wherein said common element is selected from an integrated circuit and a printed circuit board.
3 . The interposer of claim 2 further comprising one of an integrated circuit, an integrated circuit package and a printed circuit board in direct electrical contact with said lower pads.
4 . The interposer of claim 1 wherein at least one said upper connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
5 . The interposer of claim 1 wherein at least one said lower connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
6 . The interposer of claim 1 wherein at least one conduction path of said conduction paths is a functional conduction path.
7 . The interposer of claim 6 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
8 . The interposer of claim 7 wherein said resistor has a resistance of at least 10 −6 ohm to no more than 10 10 ohm.
9 . An electronic package comprising the interposer of claim 7 .
10 . An electronic device comprising the interposer of claim 7 .
11 . The interposer of claim 1 wherein said array of upper connections comprises rows and columns.
12 . The interposer of claim 11 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
13 . The interposer of claim 1 wherein said parallel plates are perpendicular to said first planar face.
14 . An electronic package comprising:
an integrated circuit comprising an array of IC contacts; a printed circuit board comprising an array of PCB contacts; and an interposer between said integrated circuit and said printed circuit board comprising: a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising:
a plurality of parallel plates with a dielectric there between;
at least one first external termination in electrical contact with a first set of alternate parallel plates; and
at least one second external termination in electrical contact with a second set of alternate parallel plates;
said capacitor is mounted on said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection; at least one upper connection, said first external termination and said second external termination are in direct electrical contact with one of said array of IC contacts and said array of PCB contacts; and said lower connections are in electrical contact with one of said array of IC contacts and said array of PCB contacts different from said upper connections.
15 . The electronic package of claim 14 wherein at least one said upper connection comprises at least one of a pin a land grid, a wire bond, a socket, a solder pad or a solder ball.
16 . The electronic package of claim 14 wherein at least one said lower connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
17 . The electronic package of claim 14 wherein at least one conduction path of said conduction paths is a functional conduction path.
18 . The electronic package of claim 17 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
19 . The electronic package of claim 17 wherein said resistor has a resistance of at least 10 −6 ohm to no more than 10 10 ohm.
20 . An electronic device comprising the electronic package of claim 18 .
21 . The electronic package of claim 14 wherein said array of upper connections comprises row and columns.
22 . The electronic package of claim 21 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
23 . The electronic package of claim 14 wherein said parallel plates are perpendicular to said planar face.
24 . An electronic device comprising:
an electronic package comprising:
an integrated circuit comprising an array of IC contacts;
a printed circuit board comprising an array of PCB contacts; and
an interposer between said integrated circuit and said printed circuit board comprising:
a first planar face and a second planar face;
an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections;
at least one capacitor comprising:
a plurality of parallel plates with a dielectric there between;
at least one first external termination in electrical contact with a first set of alternate parallel plates; and
at least one second external termination in electrical contact with a second set of alternate parallel plates;
said capacitor is mounted on said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection;
at least one upper connection, said first external termination and said second external termination are in direct electrical contact with one of said array of IC contacts and said array of PCB contacts; and
said lower contact pads are in electrical contact with one of said array of IC contacts and said array of PCB contacts different from said upper connections;
a power supply for providing power to said electronic package; an input device capable of interfacing to provide an input signal to said electronic package; and an output device capable of sending an output signal from said electronic package.
25 . The electronic device of claim 24 wherein at least one said upper connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
26 . The electronic device of claim 24 wherein at least one said lower connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
27 . The electronic device of claim 24 wherein at least one conduction path of said conduction paths is a functional conduction path.
28 . The electronic device of claim 27 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
29 . The electronic device of claim 28 wherein said resistor has a resistance of at least 10 −6 ohm to no more than 10 10 ohm.
30 . The electronic device of claim 24 wherein said array of upper connections comprises row and columns.
31 . The electronic device of claim 30 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
32 . The electronic device of claim 24 wherein said parallel plates are perpendicular to said first planar face.
33 . An interposer comprising:
a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising:
a plurality of parallel plates with a dielectric there between;
at least one first external termination in electrical contact with a first set of alternate parallel plates; and
at least one second external termination in electrical contact with a second set of alternate parallel plates;
said capacitor is electrically or physically connected to said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection wherein said parallel plates are perpendicular to said first planar face; and at least one upper connection, said first external termination and said second external termination arranged for direct electrical contact with element contact pads of a common element.
34 . The interposer of claim 33 wherein said common element is selected from an integrated circuit and a printed circuit board.
35 . The interposer of claim 34 further comprising one of an integrated circuit, an integrated circuit package and a printed circuit board in direct electrical contact with said lower pads.
36 . The interposer of claim 33 wherein at least one said upper connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
37 . The interposer of claim 33 wherein at least one said lower connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
38 . The interposer of claim 33 wherein at least on one conduction path of said conduction paths is a functional conduction path.
39 . The interposer of claim 38 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
40 . The interposer of claim 39 wherein said resistor has a resistance of at least 10 −6 ohm to no more than 10 10 ohm.
41 . An electronic package comprising the interposer of claim 39 .
42 . An electronic device comprising the interposer of claim 39 .
43 . The interposer of claim 33 wherein said array of upper connections comprises rows and columns.
44 . The interposer of claim 43 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.Cited by (0)
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