Selective etching using a hard mask and a method for forming an isolation structure of a memory device using the same

Abstract

A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed, and selectively etching the etching target layer exposed through the hard mask. The polymer preferably includes a photoresist. Also disclosed is a method for forming an isolation structure of a memory device using the selective etching method.

1 . A selective etching method comprising:
 forming a mixture comprising a polymer and carbon nanotubes;   applying the mixture on an etching target layer, thereby forming a carbon nanotube-polymer composite layer;   forming a hard mask by patterning the carbon nanotube-polymer composite layer, thereby selectively exposing a part of the etching target layer; and   selectively etching the etching target layer exposed through the hard mask.   
   
   
       2 . The selective etching method according to  claim 1 , wherein the polymer comprises a photoresist, and
 the step of forming a hard mask comprises exposing and developing the carbon nanotube-polymer composite layer.   
   
   
       3 . The selective etching method according to  claim 1 , wherein the polymer comprises an organic antireflective coating (ARC). 
   
   
       4 . A method for isolating memory cells of a memory device using a selective etching method comprising:
 forming a tunneling dielectric layer on a semiconductor substrate;   forming a charge storage layer on the tunneling dielectric layer;   forming a pad layer on the charge storage layer;   forming a composite layer of carbon nanotubes and a polymer as a hard mask on the pad layer;   sequentially selectively etching the pad layer, the charge storage layer, the tunneling dielectric layer, and the semiconductor substrate, each exposed through the hard mask, to form a trench arranged in accordance with the resulting pattern of the charge storage layer;   forming an insulating layer inside the trench to fill the trench with the insulating layer; and   planarizing the insulating layer until the pad layer is exposed, thereby isolating each memory cell.   
   
   
       5 . The method according to  claim 4 , wherein the polymer comprises a photoresist. 
   
   
       6 . The method according to  claim 4 , wherein the polymer comprises an organic antireflective coating (ARC) material. 
   
   
       7 . The method according to  claim 4 , wherein the pad layer comprises a silicon nitride layer, and the method further comprises forming a silicon oxide layer having a thickness smaller than the thickness of the silicon nitride layer as a sub hard mask at the interface between the pad layer and the hard mask. 
   
   
       8 . The method according to  claim 4 , wherein the charge storage layer comprises a conductive polysilicon layer capable of storing electrons injected by tunneling into the tunneling dielectric layer to form a control gate of a flash memory device. 
   
   
       9 . A method for forming an isolation structure of a memory device having memory cells using a selective etching method comprising:
 forming a tunneling dielectric layer on a semiconductor substrate;   forming a charge storage layer on the tunneling dielectric layer;   forming a pad layer on the charge storage layer;   forming a mixture comprising a photoresist and carbon nanotubes;   coating the mixture on the pad layer, thereby forming a carbon nanotube-photoresist composite layer;   exposing and developing the composite layer, thereby forming a composite layer pattern as a hard mask;   sequentially selectively etching the pad layer, the charge storage layer, the tunneling dielectric layer, and the semiconductor substrate, each exposed through the hard mask, to form a trench arranged in accordance with the resulting pattern of the charge storage layer;   forming an insulating layer inside the trench to fill the trench with the insulating layer; and   planarizing the insulating layer until the pad layer is exposed thereby isolating each memory cell.   
   
   
       10 . The method according to  claim 9 , wherein the pad layer comprises a silicon nitride layer, and the method further comprises forming a silicon oxide layer having a thickness smaller than the thickness of the silicon nitride layer as a sub hard mask at the interface between the pad layer and the hard mask. 
   
   
       11 . The method according to  claim 9 , wherein the charge storage layer comprises a conductive polysilicon layer capable of storing electrons injected by tunneling into the tunneling dielectric layer to form a control gate of a flash memory device.