US2008195341A1PendingUtilityA1

System and method for determining a delay time interval of components

Assignee: IBMPriority: Jan 18, 2007Filed: Apr 18, 2008Published: Aug 14, 2008
Est. expiryJan 18, 2027(~0.5 yrs left)· nominal 20-yr term from priority
G01R 31/3016
46
PatentIndex Score
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Claims

Abstract

A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Claims

exact text as granted — not AI-modified
1 . A system for determining a delay time interval of components, comprising:
 a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval, the delay chain of components being configured to utilize a selected number of components thereof to output the delayed clock signal after the delay chain of components receives the first clock signal;   a processor operably communicating with the delay chain of components configured to specify a number of components of the delay chain of components to be activated;   a latch having a clock terminal, a data terminal, and an output terminal, the first clock signal being input into both the clock terminal and the delay chain of components, the data terminal receiving the delayed clock signal from the delay chain of components;   a circuit operably coupled to the output terminal of the latch configured to determine whether an output signal from the output terminal has a high logic value or a low logic value, the circuit being further operably coupled to the processor;   the processor further configured to iteratively increase a selected number of the components of the delay chain of components to be activated, for increasing a delay time interval between the delayed clock signal and the first clock signal, until the circuit determines that the output signal from the latch has a low logic value, the selected number being a first selected number when the output signal has the low logic value;   the processor further configured to iteratively increase the selected number of the components of the delay chain of components to be activated, for increasing the delay time interval between the delayed clock signal and the first clock signal, until the circuit determines that the output signal from the latch has a high logic value, the selected number being a second selected number when the output signal has the high logic value;   the processor further configured to calculate the first delay time interval based on the first selected number and the second selected number.   
   
   
       2 . The system of  claim 1 , wherein the processor is further configured to calculate the first delay time interval for each component of the delay chain of components, based on the first selected number, the second selected number, and a time interval of a cycle of the first clock signal. 
   
   
       3 . The system of  claim 1 , wherein the processor is further configured to calculate a desired selected number of components of the delay chain of components to be activated based on the first delay time interval for each component of the delay chain of components and a total desired delay time interval between the first clock signal and the delayed clock signal. 
   
   
       4 . The system of  claim 3 , wherein the processor is further configured to transmit a signal to the delay chain of components indicating the desired selected number of components of the delay chain of components to be activated, and the delay chain of components being further configured to activate a portion of the components of the delay chain components corresponding to the desired selected number of components. 
   
   
       5 . The system of  claim 1 , further comprising:
 an adjustable drive-current buffer operably coupled to the processor, the processor further configured to induce the adjustable drive-current buffer to output a desired output current level based on the first delay time interval.

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