Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same

Abstract

A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

1 . A planar combined structure of a gallium nitride (GaN) bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field effect transistors (MESFETs), comprising:
 (a) a substrate for crystal growth;   (b) the GaN BJT, comprising;
 a low doped n-type collector layer formed on the substrate for crystal growth; 
 a high doped p-type base layer formed on the low doped collector layer; 
 a high doped n-type emitter well region formed within the high doped p-type based layer; 
 a high doped n-type collector contact well region formed within the high doped p-type base layer; and 
 an emitter metal electrode, a base metal electrode and a collector metal electrode formed on the emitter well region, the base layer and the collector contact well region, respectively; 
   (c) the n-type MESFET formed on the substrate for crystal growth, comprising:
 a low doped n-type substrate layer formed on the substrate for crystal growth; 
 a high doped p-type buried layer formed on the low doped substrate layer; 
 a high doped n-type channel region formed with the high doped p-type buried layer; and 
 a gate Schottky metal electrode, a drain metal electrode and a source metal formed on the high doped n-type channel region; and 
   (d) a p-type MESFET formed on the crystal growth layer, comprising:
 a low doped n-type buried layer formed on the substrate for crystal growth; 
 a high doped p-type channel layer formed on the low doped n-type buried layer; and 
 a gate Schottky metal electrode, a drain metal electrode and a source metal electrode formed on the high doped p-type channel layer. 
   
   
   
       2 . The planar combined structure as claimed in  claim 1 , wherein each of the low doped n-type collector layer, the high doped p-type base layer, the high doped n-type emitter well region, the high doped n-type collector contact well region, the low doped n-type substrate layer, the high doped p-type buried layer, the high doped n-type channel region, the low doped n-type buried layer and the high doped p-type channel layer are concurrently formed by one of a molecular beam epitaxy (MBE) method and a metal-organic vapor phase epitaxy (MOVPE) methods. 
   
   
       3 . The planar combined structure as claimed in  claim 1 , wherein the substrate for crystal growth is made of one selected from the group consisting of Al 2 O 3 , SiC, ZnO, Si, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0≦x≦1 and 0≦y≦1. 
   
   
       4 . The planar combined structure as claimed in  claim 1 , wherein the crystal growth layer is made of one selected from the group consisting of SiC, ZnO, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0≦x≦1 and 0≦y≦1. 
   
   
       5 . The planar combined structure as claimed in  claim 1 , wherein each of the GaN BJT and n-type and p-type MESFETs is made of one selected from the group consisting of SiC, ZnO, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0≦x≦1 and 0≦y≦1. 
   
   
       6 . The planar combined structure as claimed in  claim 1 , wherein each of the emitter, the collector contact well region and the channel region is formed by one of an ion implantation method and an impurity diffusion method. 
   
   
       7 . The planar combined structure as claimed in  claim 1 , wherein each of the emitter metal electrode, the base metal electrode, the collector metal electrode, the respective gate Schottky metal electrodes of the n-type and p-type MESFETS, the source metal electrode and drain metal electrode is made of one selected from the group consisting of Au, Pt/Ti/Pt/Au, Ti/Al/Ti/Au, Ti/Au, Cr/Au, Pd/Au, Ti/Pd/Au, Pd/Ti/Au, Cr, Pt/Au, Ni/Au, Ta/Ti, Ti/Pt/Au, Ti/Cr/Au and Pt/Ru. 
   
   
       8 . The planar combined structure as claimed in  claim 1 , wherein the GaN BJT and n-type/p-type MESFETs are formed on the crystal growth layer concurrently. 
   
   
       9 . A method for forming a planar combined structure of a gallium nitride (GaN) bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field effect transistors (MESFETs), comprising the steps of:
 (a) growing a GaN crystal growth layer having a p-n junction by forming a GaN substrate for crystal growth having an n-type layer and a p-type layer;   (b) forming a collector layer of the GaN BJT, a substrate layer of an n-type MESFET, a buried layer of a p-type MESFET, a base layer of the GaN BJT, a buried layer of the n-type MESFET and a channel layer of the p-type MESFET;   (c) forming a collector well region of the BJT, and a collector well region of the BJT and a channel region of the n-type MESFET concurrently by using one of an ion implantation method and an impurity diffusion method;   (d) forming a base metal electrode of the BJT and a drain metal electrode and a source metal electrode of the p-type MESFET concurrently;   (e) forming an emitter metal electrode and a collector metal electrode of the BJT and a drain metal electrode and a source metal electrode of the n-type MESFET concurrently;   (f) forming a first gate Schottky metal electrode on the n-type MESFET; and   (g) forming a second gate Schottky metal electrode on the p-type MESFET.   
   
   
       10 . The method as claimed in  claim 9 , further comprising a step, between the steps (c) and (d), of activating the collector contact well of the BJT and the emitter well region/channel region of the n-type MESFET concurrently or separately by providing a high temperature.