Per byte lane dynamic on-die termination

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed.

1 . An integrated circuit comprising:
 logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect, wherein the ODT value specifies an amount of termination resistance.   
   
   
       2 . The integrated circuit of  claim 1 , wherein the plurality of integrated circuits comprises:
 a plurality of dynamic random access memory device (DRAM) in a memory system.   
   
   
       3 . The integrated circuit of  claim 2 , wherein the logic to independently program at least one ODT value for each DRAM in the memory system comprises:
 logic to determine a specific DRAM identifier for each DRAM in the memory system, wherein the DRAM identifier corresponds to a range of byte lane lengths; and   logic to program the specific DRAM identifier into a register of each DRAM in the memory system.   
   
   
       4 . The integrated circuit of  claim 3 , wherein the logic to determine a specific DRAM identifier for each DRAM in the memory system comprises:
 a lookup table specifying a plurality of DRAM identifiers and a corresponding plurality of ranges of byte lane lengths.   
   
   
       5 . The integrated circuit of  claim 2 , wherein the logic to independently program at least one ODT value for each DRAM in the memory system comprises:
 logic to issue a command for each DRAM to enter a non-operating mode;   logic to send, during a first write cycle, a DRAM identifier; and   logic to send, during a second write cycle, at least one ODT value corresponding to the DRAM identifier.   
   
   
       6 . The integrated circuit of  claim 5 , wherein
 the command is a mode register set (MRS) command and the non-operating mode is an MRS WRITE mode.   
   
   
       7 . The integrated circuit of  claim 6 , wherein the logic to send, during the second write cycle, at least one ODT value corresponding to the DRAM identifier comprises:
 logic to send a first ODT value and a second ODT value, wherein the first ODT value corresponds to an active state and the second ODT value corresponds to a passive state.   
   
   
       8 . The integrated circuit of  claim 1 , wherein the integrated circuit comprises a memory controller. 
   
   
       9 . The integrated circuit of  claim 8 , wherein the integrated circuit further comprises a processor. 
   
   
       10 . A method comprising:
 receiving, at a memory device, a command instructing the memory device to enter a non-operating mode;   receiving, during a first write cycle, a memory device identifier;   comparing the received DRAM identifier with a stored value; and   entering the non-operating mode, if the received memory device identifier matches the stored value.   
   
   
       11 . The method of  claim 10 , further comprising:
 receiving at the memory device, during a subsequent write cycle, data specifying at least one on-die termination (ODT) value; and   programming a register with the data specifying the at least one ODT value.   
   
   
       12 . The method of  claim 11 , wherein the memory device is a dynamic random access memory device (DRAM). 
   
   
       13 . The method of  claim 12 , wherein the command is a mode register set (MRS) command. 
   
   
       14 . The method of  claim 13 , wherein the register is a multipurpose register (MPR). 
   
   
       15 . A system comprising:
 a plurality of memory devices coupled with an interconnect; and   an integrated circuit coupled with the interconnect, the integrated circuit including logic to independently program at least one on-die termination (ODT) value for each of a plurality of the plurality of memory devices, wherein the ODT value specifies an amount of termination resistance.   
   
   
       16 . The system of  claim 15 , wherein the plurality of memory devices is a plurality of dynamic random access memory devices (DRAMs). 
   
   
       17 . The system of  claim 15 , wherein the logic to independently program at least one ODT value for each DRAM comprises:
 logic to determine a specific DRAM identifier for each DRAM in the memory system, wherein the DRAM identifier corresponds to a range of byte lane lengths; and   logic to program the specific DRAM identifier into a register of each DRAM in the memory system.   
   
   
       18 . The system of  claim 17 , wherein the logic to determine a specific DRAM identifier for each DRAM in the memory system comprises:
 a lookup table specifying a plurality of DRAM identifiers and a corresponding plurality of ranges of byte lane lengths.   
   
   
       19 . The system of  claim 16 , wherein the logic to independently program at least one ODT value for each DRAM in the memory system comprises:
 logic to issue a command for each DRAM to enter a non-operating mode;   logic to send, during a first write cycle, a DRAM identifier; and   logic to send, during a second write cycle, at least one ODT value corresponding to the DRAM identifier.   
   
   
       20 . The system of  claim 19 , wherein
 the command is a mode register set (MRS) command and the non-operating mode is an MRS WRITE mode.