Semiconductor integrated circuit

Abstract

The semiconductor integrated circuit ( 1 ) has a memory ( 4 ) and a logic circuit ( 5 ), which are mixedly palletized on a silicon substrate ( 2 ). The memory includes a partially-depleted type nMOS ( 6 ) having an SOI structure and formed on UTB ( 3 ). The partially-depleted type nMOS has a backgate region ( 14 ) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS ( 7 ) and a pMOS ( 8 ), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions ( 14, 22 ) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

1 . A semiconductor integrated circuit comprising:
 a first MOS transistor of a partially-depleted type; and   second MOS transistors of a fully-depleted type, the first and second MOS transistors having an SOI structure separated electrically and formed on respective insulating films,   wherein the first MOS transistor has a first semiconductor region under the insulating film, to which a voltage can be applied independently of a gate terminal thereof,   the second MOS transistors have second semiconductor regions under the insulating films, to which voltages can be applied independently of gate terminals thereof,   the first MOS transistor forms a storage device holding information by a first state that an excessive amount of carriers is accumulated in a third semiconductor region for forming a channel and a second state that the excessive amount of carriers is discharged from the third semiconductor region, and   the second transistors form a logic circuit.   
     
     
         2 . The semiconductor integrated circuit of  claim 1 , further comprising:
 a fourth semiconductor region disposed between the first semiconductor region and a semiconductor substrate when the first semiconductor region is coincident in conductivity type with the semiconductor substrate, and having a conductivity type differing from the conductivity type of the semiconductor substrate; and   a fifth semiconductor region coincident in conductivity type with the fourth semiconductor region, and used for applying a voltage to the fourth semiconductor region.   
     
     
         3 . The semiconductor integrated circuit of  claim 1 , further comprising:
 a sixth semiconductor region disposed between the second semiconductor region and a semiconductor substrate when the second semiconductor region is coincident in conductivity type with the semiconductor substrate, and having a conductivity type differing from the conductivity type of the semiconductor substrate; and   a seventh semiconductor region coincident in conductivity type with the sixth semiconductor region, and used for applying a voltage to the sixth semiconductor region.   
     
     
         4 . The semiconductor integrated circuit of  claim 1 , further comprising third MOS transistors having a bulk structure,
 wherein the third MOS transistors each have an eighth semiconductor region for forming a channel, and   the eighth semiconductor regions each have a ninth semiconductor region to which a voltage can be applied independently of a gate terminal of the corresponding third MOS transistor.   
     
     
         5 . The semiconductor integrated circuit of  claim 4 , wherein the third MOS transistors form an input-protection device connected to an external input terminal, and
 the input-protection device has an nMOS with a gate connected to a ground terminal and a pMOS with a gate connected to a power-supply terminal.   
     
     
         6 . The semiconductor integrated circuit of  claim 4 , further comprising:
 a tenth semiconductor region disposed between the eighth semiconductor region and the semiconductor substrate when the eighth semiconductor region is coincident in conductivity type with the semiconductor substrate, and having a conductivity type differing from the conductivity type of the semiconductor substrate; and   an eleventh semiconductor region coincident in conductivity type with the tenth semiconductor region, and used for applying a voltage to the tenth semiconductor region.   
     
     
         7 . A semiconductor integrated circuit comprising:
 a first MOS transistor of a partially-depleted type; and   second MOS transistors of a fully-depleted type, the first and second MOS transistors having an SOI structure separated electrically and formed on respective first insulating films, the first MOS transistor having a first semiconductor region under the first insulating film, to which a voltage can be applied independently of a gate terminal thereof, and the second MOS transistors having second semiconductor regions under the first insulating films, to which voltages can be applied independently of gate terminals thereof;   a second insulating film disposed between the first and second semiconductor regions and a semiconductor substrate,   wherein the first MOS transistor forms a storage device holding information by a first state that an excessive amount of carriers is accumulated in a third semiconductor region for forming a channel and a second state that the excessive amount of carriers is discharged from the third semiconductor region, and   the second MOS transistors form a logic circuit.   
     
     
         8 . A semiconductor integrated circuit comprising:
 a first semiconductor integrated circuit; and   a second semiconductor integrated circuit, the first and second semiconductor integrated circuits each prepared by removing the semiconductor substrate from under the second insulating film of the semiconductor integrated circuit of  claim 7 ,   wherein one of the first and second semiconductor integrated circuits is stacked on the other.   
     
     
         9 . The semiconductor integrated circuit of  claim 8 , further comprising:
 a first winding using a conductor line on the first semiconductor integrated circuit; and   a second winding using a conductor line on the second semiconductor integrated circuit,   wherein the first and second semiconductor integrated circuits are coupled with each other by the first and second windings electromagnetically.   
     
     
         10 . The semiconductor integrated circuit of  claim 8 , further comprising:
 a first electrode provided on the first semiconductor integrated circuit; and   a second electrode provided on the second semiconductor integrated circuit and opposed to the first electrode,   wherein the first and second semiconductor integrated circuits are capacitively coupled by the first and second electrodes.   
     
     
         11 . The semiconductor integrated circuit of  claim 8 , further comprising:
 a light-emitting device provided on the first semiconductor integrated circuit; and   a light-receiving device provided on the second semiconductor integrated circuit,   wherein the first and second semiconductor integrated circuits use the light-emitting device and light-receiving device to perform optical communication.   
     
     
         12 . The semiconductor integrated circuit of  claim 2 , further comprising a third MOS transistor having a bulk structure,
 wherein an eighth semiconductor region for forming a channel of the third MOS transistor has a ninth semiconductor region to which a voltage can be applied independently of a gate terminal of the third MOS transistor.   
     
     
         13 . The semiconductor integrated circuit of  claim 3 , further comprising a third MOS transistor having a bulk structure,
 wherein an eighth semiconductor region for forming a channel of the third MOS transistor has a ninth semiconductor region to which a voltage can be applied independently of a gate terminal of the third MOS transistor.   
     
     
         14 . The semiconductor integrated circuit of  claim 5 , further comprising:
 a tenth semiconductor region disposed between the eighth semiconductor region and a semiconductor substrate when the eighth semiconductor region is coincident in conductivity type with the semiconductor substrate, and having a conductivity type differing from the conductivity type of the semiconductor substrate; and   an eleventh semiconductor region coincident in conductivity type with the tenth semiconductor region, and used for applying a voltage to the tenth semiconductor region.