Auto Software Configurable Register Address Space For Low Power Programmable Processor

Abstract

A configurable graphics pipeline has more than one possible process flow of pixel packets through elements of the graphics pipeline. In one embodiment, a data packet triggers an element of the graphics pipeline to discover an identifier.

1 . A method of configuring a plurality of Arithmetic Logic Units (ALUs) within a programmable ALU stage of a configurable graphics pipeline having more than one possible process flow of pixel packets through the ALUs of said programmable ALU stage, the method comprising:
 initiating the generation of an identification packet within said programmable ALU stage,   the identification packet flowing between elements of the programmable ALU stage and triggering said ALUs of said graphics pipeline to discover an identifier for each ALU indicative of the location of the ALU within a process flow; and   wherein the generation of the initial identification packet triggers the ALUs to discover their relative location with the process flow without requiring a direct register write of each ALU.   
   
   
       2 . The method of  claim 1 , wherein said identification packet triggering said ALUs is generated in response to a software command from a software entity. 
   
   
       3 . The method of  claim 1 , wherein each ALU in response to the identification packet writes an identifier in a configuration register indicative of an execution order within said process flow. 
   
   
       4 . The method of  claim 1 , wherein each ALU writes a current value of an identifier of said identification packet into a configuration register of the ALU, increments said identifier, and forwards said identification packet to the next ALU. 
   
   
       5 . The method of  claim 4 , wherein a software entity initiates the identification packet to trigger the ALUs to discover their relative location with the process flow without requiring a direct register write of each ALU. 
   
   
       6 . The method of  claim 1 , wherein a software entity initiates the identification packet to trigger the ALUs to discover their relative location with the process flow without requiring a direct register write of each ALU. 
   
   
       7 . A graphics processor, comprising:
 a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets, said ALU stage including a plurality of ALUs with each ALU including a configuration register to store an identifier indicative of an execution order of the ALU within a process flow, each ALU having a set of at least one possible arithmetic operation that is performed on an incoming pixel packet having a corresponding current instruction command;   a data fetch stage to fetch data for said pixel packets;   a data write stage to perform a memory write of pixel data of processed pixel packets received from said ALU stage;   a first distributor coupled to respective inputs of said ALU stage, said data fetch stage, and said data write stage; and   a second distributor coupled to respective outputs of said ALU stage, said data fetch stage, and said data write stage;   said first distributor and said second distributor adapted for reconfiguring a process flow of pixel packets through said data fetch stage, said ALU stage, and said ALU write stage in response to a command from a host;   wherein each ALU of said ALU stage is configured to receive an identification packet initiated by a software entity, each ALU writing a current value of an identifier of said identification packet into the configuration register of the ALU, incrementing said identifier, and forwarding said identification packet to the next ALU; wherein the software entity initiates the identification packet to trigger the ALUs to discover their relative location with the process flow without requiring a direct register write of each ALU.   
   
   
       8 . The graphics processor of  claim 7 , wherein said ALU stage is configured to execute a shader program. 
   
   
       9 . The graphics processor of  claim 7  wherein the execution order determines a sequence in which a plurality of ALUs are programmed to read operands, generate arithmetic results, and update one or more pixel packets or temporary values before passing on a row of pixel packets to the next ALU. 
   
   
       10 . The graphics processor of  claim 7 , wherein the execution order determines the processing task performed by each ALU. 
   
   
       11 . A method of configuring a plurality of Arithmetic Logic Units (ALUs) within a programmable ALU stage of a configurable graphics pipeline having more than one possible process flow of pixel packets through the ALUs of said programmable ALU stage, the method comprising:
 a software entity initiating the injection of an identification packet into said programmable ALU stage of said configurable graphics pipeline;   each successive ALU within the programmable ALU stage reading a current value of an identifier in said identification packet, writing said current value to a configuration register within the ALU, incrementing said identifier, and forwarding said identification packet with an incremented identifier to the next ALU of said programmable ALU stage; and   the identifier with each ALU being indicative of an execution order within a process flow with the software entity initiating the identification packet to trigger the ALUs to discover their relative location with the process flow without requiring a direct register write of each ALU.   
   
   
       12 . The method of  claim 11 , wherein said identification packet is initiated in response to a software command from the software entity. 
   
   
       13 . The graphics processor of  claim 11 , wherein said ALU stage is configured to execute a shader program. 
   
   
       14 . The graphics processor of  claim 11 , wherein the execution order determines a sequence in which a plurality of ALUs are programmed to read operands, generate arithmetic results, and update one or more pixel packets or temporary values before passing on a row of pixel packets to the next ALU. 
   
   
       15 . The graphics processor of  claim 11 , wherein the execution order determines the processing task performed by each ALU.