High voltage LDMOS

Abstract

A power semiconductor device having high avalanche capability comprises an N + doped substrate and, in sequence, N − doped, P − doped, and P + doped semiconductor layers, the P − and P + doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N − and P − doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N − doped epitaxial layer on an N + doped substrate, forming a P − doped layer in the N − doped epitaxial layer, forming a P + doped layer in the P − doped layer, and forming in the P − and N − doped layers recombination centers comprising noble metal impurities. The P + and P − doped layers have a combined thickness of about 5 μm to about 12 μm.

1 . A power semiconductor device comprising:
 a semiconductor substrate with two surfaces, an N+ doped layer extending into the substrate from one surface thereof, an N− doped layer over the N+ doped layer, a P− doped well formed in the N− doped layer and extending from the other surface of the substrate into the N− doped layer, the P− doped well having a first thickness and forming a first boundary with the N− doped layer, a P+ doped region formed in the P− doped well and extending from the other surface of the substrate into the P− doped well having a second thickness and forming a second boundary between the P+ doped region and the P− doped well, an N+ doped region formed in the other surface of the substrate, the N+ doped region having a third thickness and forming a third boundary between the N+ doped region and the P-well,   wherein the P+ doped region is vertically thinner than the P− doped well and vertically thinner than the N+ doped region, and   recombination centers comprising noble metal impurities disposed in the N− doped layer and the P− doped well.   
   
   
       2 . The device of  claim 1  wherein the ratio of thickness of the P+ doped region to the P− doped well is between 1:40 and 1:5. 
   
   
       3 . The device of  claim 2  wherein the P+ doped region is between 0.1 and 2.0 μm thick and the P− doped well is between 4.0 and 10.0 μm thick. 
   
   
       4 . The device of  claim 1   wherein the third boundary is between the N+ doped region and the P− doped well; and   wherein the N+ doped region is within the P− doped well.   
   
   
       5 . The device of  claim 4   wherein the third boundary is between the N+ doped region and the P− doped well; and   wherein the N+ doped region abuts the P+ doped region.   
   
   
       6 . The device of  claim 1  wherein the P− doped well has a thickness of about 4 μm to about 10 μm. 
   
   
       7 . The device of  claim 1  wherein the P+ doped region has a thickness of about 0.1 μm to about 2 μm. 
   
   
       8 . The device of  claim 1  wherein the P− doped well has a dopant level of at least 10 16  atoms/cm 3 . 
   
   
       9 . The device of  claim 8  wherein the P− doped well has a dopant level of about 2.5×10 17  atoms/cm 3 . 
   
   
       10 . The device of  claim 1  wherein the P+ doped region has a dopant level of at least 10 18  atoms/cm 3 . 
   
   
       11 . The device of  claim 10  wherein the P+ doped region has a dopant level of about 6×10 19  atoms/cm 3 . 
   
   
       12 . The device of  claim 1  wherein the N− doped layer has a dopant level of about 10 14  atoms/cm 3  to about 10 15  atoms/cm 3 . 
   
   
       13 . The device of  claim 1  wherein the noble metal impurities are selected from the group consisting of gold, platinum, and palladium. 
   
   
       14 . The device of  claim 13  wherein the noble metal impurities comprise platinum. 
   
   
       15 . The device of  claim 14  wherein the recombination centers are formed by platinum diffusion through the one surface of the substrate into the N− doped layer and P− doped well. 
   
   
       16 . The device of  claim 14  containing platinum impurities at a concentration of about 1×10 15  to about 1×10 16  atoms/cm 3 . 
   
   
       17 . The device of  claim 16  wherein the concentration of platinum impurities is about 2×10 15  atoms/cm 3 . 
   
   
       18 . The device of  claim 1  comprising a MOSFET or an IGBT power device.