SOI field effect transistor and corresponding field effect transistor

Abstract

A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.

1 . A first SOI field effect transistor with predetermined transistor properties, comprising:
 a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate;   a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and   two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor,   wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.   
   
   
       2 . The first SOI field effect transistor as claimed in  claim 1 , wherein the length of the channel region between the two source/drain regions, the threshold voltage, the leakage current characteristic, the maximum current, and/or a transistor characteristic curve is set as the predetermined transistor properties. 
   
   
       3 . The first SOI field effect transistor as claimed in  claim 1 , wherein the thickness of the spacer layer is set by forming the spacer layer using a chemical vapor deposition method or an atomic layer deposition method. 
   
   
       4 . The first SOI field effect transistor as claimed in  claim 1 , wherein the two source/drain regions are formed using an ion implantation method or a diffusion method, and the dopant concentration profile is set by choosing the type, the concentration, and/or the diffusion properties of the dopant atoms. 
   
   
       5 . The first SOI field effect transistor as claimed in  claim 1 , wherein the predetermined transistor properties of the first SOI field effect transistor are set by selecting the material of the gate region, the dopant concentration of the substrate, and/or the dopant profile of the substrate. 
   
   
       6 . The first SOI field effect transistor as claimed in  claim 5 , wherein the dopant profile of the substrate is set using a pocket doping and/or a retrograde well. 
   
   
       7 . The first SOI field effect transistor as claimed in  claim 1 , further comprising a second SOI field effect transistor formed similar to the first SOI field effect transistor on and/or in the substrate, wherein the predetermined transistor properties of the second SOI field effect transistor are different from those of the first SOI field effect transistor. 
   
   
       8 . The first SOI field effect transistor as claimed in  claim 7 , wherein the different transistor properties of the first SOI field effect transistor and of the second SOI field effect transistor result solely from different thicknesses of the spacer layers. 
   
   
       9 . The first SOI field effect transistor as claimed in  claim 1 , further comprising a third SOI field effect transistor formed similar to the first SOI field effect transistor on and/or in the substrate,
 wherein the predetermined transistor properties of the third SOI field effect transistor are analogous to those of the first SOI field effect transistor, and the conduction types of the first SOI field effect transistor and the third SOI field effect transistor are complementary to one another.   
   
   
       10 . The first SOI field effect transistor as claimed in  claim 7 , further comprising a third SOI field effect transistor formed similar to the first SOI field effect transistor on and/or in the substrate,
 wherein the predetermined transistor properties of the third SOI field effect transistor are analogous to those of the first SOI field effect transistor, and the conduction types of the first SOI field effect transistor and the third SOI field effect transistor are complementary to one another.   
   
   
       11 . The first SOI field effect transistor as claimed in  claim 7 , wherein the gate regions of the first SOI field effect transistor and of the second SOI field effect transistor or of the first SOI field effect transistor, of the second SOI field effect transistor, and of the third SOI field effect transistor are produced from the same material. 
   
   
       12 . The first SOI field effect transistor as claimed in  claim 11 , wherein the material of the gate regions has a value of a work function which is essentially equal to an arithmetic mean of values of a work function of heavily p-doped polysilicon and heavily n-doped polysilicon. 
   
   
       13 . The first SOI field effect transistor as claimed in  claim 11 , wherein the material of the gate regions is germanium, tungsten, tantalum, and/or titanium nitride. 
   
   
       14 . The first SOI field effect transistor as claimed in  claim 12 , wherein the material of the gate region has a work function of between 4.45 electron volts and 4.95 electron volts. 
   
   
       15 . The first SOI field effect transistor as claimed in  claim 7 , wherein the predetermined transistor properties of the first SOI field effect transistor and of the second SOI field effect transistor are such that one of the two SOI field effect transistors is optimized for a low leakage current and the other for a low threshold voltage. 
   
   
       16 . The first SOI field effect transistor as claimed in  claim 1 , wherein at least one SOI field effect transistor is a vertical transistor, a transistor having at least two gate terminals, or a fin-FET. 
   
   
       17 . The first SOI field effect transistor as claimed in  claim 7 , further comprising a protective layer that protects the second SOI field effect transistor from doping during a formation of the source/drain regions of the first SOI field effect transistor, and/or a protective layer that protects the first SOI field effect transistor from doping during a formation of the source/drain regions of the second SOI field effect transistor. 
   
   
       18 . The first SOI field effect transistor as claimed in  claim 7 , wherein at least one of the SOI field effect transistors has at least one additional spacer layer on the spacer layer.