US2008217677A1PendingUtilityA1

Non-volatile semiconductor memory device with alternative metal gate material

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Assignee: SAMSUNG ELECTRICPriority: Oct 8, 2004Filed: May 14, 2008Published: Sep 11, 2008
Est. expiryOct 8, 2024(expired)· nominal 20-yr term from priority
H10D 30/69H10D 30/681H10D 64/685H10D 64/037H10D 64/035G11C 16/0416G11C 16/0466
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Claims

Abstract

A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

Claims

exact text as granted — not AI-modified
1 . A non-volatile semiconductor memory device, comprising:
 a substrate, said substrate including a source region, a drain region and a channel region provided between said source region and said drain region; and   a gate stack located above said channel region, said gate stack including a sequential stack of a tunnel layer, a charge trapping layer, a charge blocking layer and a control gate, wherein said tunnel layer is adjacent to said channel region,   wherein said control gate is metal gate comprised of a metal having a specific metal work function equal or greater than 4.4 eV wherein the blocking layer includes SiO 2 ,   wherein the memory device is a floating gate memory device and the charge trapping layer is a floating gate, and   wherein said floating gate is a metal gate comprised of a metal having a specific metal work function equal or greater than 4.9 eV, and wherein the tunnel layer is a high-k dielectric.   
   
   
       2 . The non-volatile semiconductor memory device of  claim 1 , wherein said gate stack comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: O/SiN/SiO 2 /M, O/H/SiO 2 /M, H/H/SiO 2 /M, or H/SiN/SiO 2 /M, where O is an oxide material, H is a high κ material and M is a metal having said specific work function. 
   
   
       3 . The non-volatile semiconductor memory device of  claim 1 , wherein said tunnel layer is a dielectric selected from the group consisting of SiO 2 , Al 2 O 3 , MgO, SrO, SiN, BaO, TiO, Si 3 N 4 , Ta 2 O 5 , BaTiO 3 , BaZrO, ZrO 2 , HfO 2 , Al 2 O 3 , Y 2 O 3 , ZrSiO, HfSiO, and LaAlO 3 . 
   
   
       4 . The non-volatile semiconductor memory device of  claim 1 , wherein said floating gate comprising a material selected from the group consisting of polysilicon, platinum (Pt), gold (Au), titanium-aluminium alloy (TiAlN), and palladium (Pd) and a metal composite group consisting of metal nitride, metal boron nitride, metal silicon nitride, metal aluminium nitride and metal silicide. 
   
   
       5 . The non-volatile semiconductor memory device of  claim 1 , wherein said substrate is a Si substrate.

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