Synchronous first-in/first-out block memory for a field programmable gate array

Abstract

The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

1 . A field programmable gate array comprising:
 a plurality of random access memory clusters that store data;   a plurality of static random access memory blocks that control transmission of data to and from said plurality of random access memory clusters wherein each of said plurality of random access memory clusters are coupled to one said plurality of static random access memory blocks; and   a plurality of dedicated first-in/first-out memory logic components for providing first-in/first out access to said data stored in said plurality of random access memory clusters wherein each of said plurality of plurality of dedicated first-in/first-out memory logic components is coupled to one of said plurality of static random access memory blocks and to each of said plurality of random access memory clusters coupled to said one of said plurality of static random access memory blocks.